• Title/Summary/Keyword: 기억소자

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A study on Dynamic Characteristics of the Robot Hand Using the Segmented Binary Control (구간분할 바이너리 제어를 이용한 로봇핸드의 동특성에 관한 연구)

  • Jeong Sanghwa;Cha Kyoungrae;Kim Hyunuk;Choi Sukbong;Kim Gwangho;Park Juneho
    • Proceedings of the Korean Society of Machine Tool Engineers Conference
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    • 2005.05a
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    • pp.144-149
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    • 2005
  • In recent years, as the robot technology is developed the researches on the artificial muscle actuator that enable robot to move dextrously like biological organ become active. The widely used materials for artificial muscle are the shape memory alloy and the electroactive polymer. These actuators have the higher energy density than the electromechanical actuator such as motor. However, there are some drawbacks for actuator. SMA has the hysterical dynamic characteristics. In this paper the segmented binary control for reducing the hysteresis of SMA is proposed and the simulation of anthropomorphic robotic hand is performed using ADAMS.

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Durability of the Flexible Shape Memory Device (형상 기억 유연 소자의 내구성 평가에 관한 연구)

  • Yang, Hee-Kyung;Kim, Hae-Jin;Kim, Dae-Eun
    • Transactions of the Society of Information Storage Systems
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    • v.11 no.2
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    • pp.36-40
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    • 2015
  • The demand for flexible devices including solar cells, memories and batteries has increased rapidly over the past decades. In most flexible devices, polymer-based materials are used to enable the mechanical deformations such as bending or folding. Shape Memory Polymers (SMPs) is a high molecular compound polymer with flexibility and shape recovery characteristics. In this work, flexible shape memory device was fabricated by simply coating the conducting material, carbon nano-tube (CNT), on a shape memory polymer. Furthermore, durability of the device under various type of mechanical deformations was assessed. It is believed that the result of this work will aid in realization of a stretchable and wearable electronic device for practical applications.

A Study on the Dynamic Characteristics of Robot Hand based on Segmented Control (구간분할 제어를 이용한 로봇핸드의 동특성에 관한 연구)

  • Jeong S.H.;Kim H.U.;Choi S.B.;Kim G.H.;Park J.H.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2005.10a
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    • pp.310-313
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    • 2005
  • In recent years, as the robot technology is developed, the researches on the artificial muscle actuator that enable robot to move dexterously like biological organ become active. The widely used materials for artificial muscle are the shape memory alloy and the electro-active polymer. These actuators have the higher energy density than the electro-mechanical actuator such as motor. However, there are some drawbacks for actuator. SMA has the hysterical dynamic characteristics. In this paper, the simulation of anthropomophic robotic hand is performed using ADAMS and the segmented binary control for reducing the hysteresis of SMA is proposed. SMA is controlled by thermo-electric module. The relations between the force and the hysteresis are developed to verify the validity of the suggested method.

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Design of 3-bit Arbitrary Logic Circuit based on Single Layer Magnetic-Tunnel-Junction Elements (단층 입력 구조의 Magnetic-Tunnel-Junction 소자를 이용한 임의의 3비트 논리회로 구현을 위한 자기논리 회로 설계)

  • Lee, Hyun-Joo;Kim, So-Jeong;Lee, Seung-Yeon;Lee, Seung-Jun;Shin, Hyung-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.12
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    • pp.1-7
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    • 2008
  • Magnetic Tunneling Junction (MTJ) has been used as a nonvolatile universal storage element mainly in memory technology. However, according to several recent studies, magneto-logic using MTJ elements show much potential in substitution for the transistor-based logic device. Magneto-logic based on MTJ can maintain the data during the power-off mode, since an MTJ element can store the result data in itself. Moreover, just by changing input signals, the full logic functions can be realized. Because of its programmability, it can embody the reconfigurable magneto-logic circuit in the rigid physical architecture. In this paper, we propose a novel 3-bit arbitrary magneto-logic circuit beyond the simple combinational logic or the short sequential one. We design the 3-bit magneto-logic which has the most complexity using MTJ elements and verify its functionality. The simulation results are presented with the HSPICE macro-model of MTJ that we have developed in our previous work. This novel magneto-logic based on MTJ can realize the most complex logic function. What is more, 3-bit arbitrary logic operations can be implemented by changing gate signals of the current drivel circuit.

Design of 4-bit Gray Counter Simulated with a Macro-Model for Single-Layer Magnetic-Tunnel-Junction Elements (단층 입력 구조의 Magnetic-Tunnel-Junction 소자용 Macro-Model을 이용한 4비트 그레이 카운터의 설계)

  • Lee, Seung-Yeon;Lee, Gam-Young;Lee, Hyun-Joo;Lee, Seung-Jun;Shin, Hyung-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.9
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    • pp.10-17
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    • 2007
  • It opens a new horizon on spintronics for the potential application of MTJ as a universal logic element, to employ the magneto-logic in substitution for the transistor-based logic device. The magneto-logic based on the MTJ element shows many potential advantages, such as high density, and nonvolatility. Moreover, the MTJ element has programmability and can therefore realize the full logic functions just by changing the input signals. This magneto-logic using MTJ elements can embody the reconfigurable circuit to overcome the rigid architecture. The established magneto-logic element has been designed and fabricated on a triple-layer MTJ. We present a novel magneto-logic structure that consists of a single layer MTJ and a current driver, which requires less processing steps with enhanced functional flexibility and uniformity. A 4-bit gray counter is designed to verify the magneto-logic functionality of the proposed single-layer MTJ and the simulation results are presented with the HSPICE macro-model of MTJ that we have developed.

A Study on Poly-Si TFT characteristics with string structure for 3D SONOS NAND Flash Memory Cell (3차원 SONOS 낸드 플래쉬 메모리 셀 적용을 위한 String 형태의 폴리실리콘 박막형 트랜지스터의 특성 연구)

  • Choi, Chae-Hyoung;Choi, Deuk-Sung;Jeong, Seung-Hyun
    • Journal of the Microelectronics and Packaging Society
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    • v.24 no.3
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    • pp.7-11
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    • 2017
  • In this paper, we have studied the characteristics of NAND Flash memory in SONOS Poly-Si Thin Film Transistor (Poly-Si TFT) device. Source/drain junctions(S/D) of cells were not implanted and selective transistors were located in the end of cells. We found the optimum conditions of process by means of the estimation for the doping concentration of channel and source/drain of selective transistor. As the doping concentration was increased, the channel current was increased and the characteristic of erase was improved. It was believed that the improvement of erase characteristic was probably due to the higher channel potential induced by GIDL current at the abrupt junction. In the condition of process optimum, program windows of threshold voltages were about 2.5V after writing and erasing. In addition, it was obtained that the swing value of poly Si TFT and the reliability by bake were enhanced by increasing process temperature of tunnel oxide.

Electro-fatigue Characteristic of Shape Memory Alloy Applied to the Electrosurgical Knee Wand of Variation of Wand Head Angle in Electrosurgical Knee Surgeries (헤드각이 변화하는 Electrosurgical Knee Wand에 적용된 형상기억합금 스프링의 전기적 피로특성)

  • An, Jae-Uk;Kim, Cheol-Woong;Lee, Ho-Sang;Wang, Joon-Ho;Oh, Dong-Joon
    • Proceedings of the KSME Conference
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    • 2008.11a
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    • pp.1547-1552
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    • 2008
  • The tip of these catheter with straight needles is not able to reach in the vicinity of the disc bulging, which are the cause of the low back pain and because the far indirect radio-frequency treatment results in the decompression, the nucleoplasty has the limit. Many incurable diseases has not been solved due to the unexistence of the advanced technique for the MIS human body catheter device. To increase the possibility of nucleoplasty, the needle tip should be located at the closest area of the lesion. For this reason, the best way to increase the success rate of the operation is that the needle tip should access 3-dimensionally to the operating field as soon as possible. To achieve this aim, our studies are restricted as follows: 1) the SMA catheter design to control the 3-dimensional direction, 2) the security of the immediate response by the positive control of the SMA element thermal distribution using Peltier thermoelectric elements, 3) the aquisition of the control data by monitoring the relationship between the temperature of SMA element and the displacement, and 4) the design of the controller to guarantee the accurate location.

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MOCVD 법에 의한 Ruthenium 박막의 증착 및 특성 분석

  • 강상열;최국현;이석규;황철성;석창길;김형준
    • Proceedings of the Korean Vacuum Society Conference
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    • 1999.07a
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    • pp.152-152
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    • 1999
  • 1Gb급 이상 기억소자의 캐패시터 재료로 주목받고 있는 (Ba,Sr)TiO3 [BST] 박막의 전극재료로는 Pt, Ru, Ir과 같은 금속전극과 RuO2, IrO2와 산화물 전도체가 유망한 것으로 알려져 있다. 그런데, DRAM의 집적도가 증가하게 되면, BST같은 고유전율 박막을 유전재료로 사용한다 하더라도, 3차원적인 구조가 불가피하게 때문에 기존의 sputtering 방법으로는 우수한 단차피복성을 얻기 힘들므로, MOCVD법이 필수적이다. 본 연구에서는 기존에 연구되었던 Pt에 비해 식각특성이 우수하고, 비교적 낮은 비저항을 갖는 Ru 박막증착에 대한 연구를 행하였다. 본 연구에서는 수직형의 반응기와 저항 가열 방식의 susceptor로 구성된 저압 유기금속 화학증착기를 사용하여 최대 6inch 직경을 갖는 기판 위에 Ru박막을 증착하였다. Precursor로는 기존에 연구된 적이 없는 bis-(ethyo-$\pi$-cyclopentadienyl)Ru (Ru(C5H4C2H5)2, [Ru(EtCp)2])를 사용하였으며, bubbler의 온도는 85$^{\circ}C$로 하였다. Si, SiO2/Si를 사용하였으며, 증착온도 25$0^{\circ}C$~40$0^{\circ}C$, 증착압력 3Torr의 조건에서 Ru 박막을 증착하였다. Presursor를 운반하는 수송기체로는 Ar을 사용하였으며, carbon과 같은 불순물의 제거를 위해 O2를 첨가하였다. 증착된 박막은 XRD, SEM, 4-point probe등을 통해 구조적, 전기적 특성을 평가하였으며, 열역학 계산을 위해서는 SOLGASMIX-PV프로그램을 사용하였다. Ru 박막의 증착에 있어서 산소의 첨가는 필수적이었으며, Ru 박막의 증착속도는 30$0^{\circ}C$~40$0^{\circ}C$의 온도 영역에서 200$\AA$/min으로 일정하였으며, 첨가된 산소의 양이 적을수록 더 치밀하고 평탄한 표면형상을 보였으며, 또한 더 낮은 전기 전도도를 보였다. 그리고 증착된 박막은 12~15$\mu$$\Omega$cm 정도의 낮은 비저항 값을 나타냈으며 이것은 기존의 sputtering 법에 의해 증착된 Ru 박막의 비저항 값들과 비교될만하다. 한편, 높은 온도, 높은 산소분압 조건에서 RuO2의 형성을 관찰하였으며, 이것은 열역학적인 계산을 통해서 잘 설명할 수 있었다.

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A Study on the Abnormal Oxidation of Stacked Capacitor due to Underlayer Dependent Nitride Deposition (질화막 성장의 하지의존성에 따른 적층캐패시터의 이상산화에 관한 연구)

  • 정양희
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.1
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    • pp.33-40
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    • 1998
  • The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

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A Study on the Characteristics of Si-$SiO_2$ interface in Short channel SONOSFET Nonvolatile Memories (Short channel SONOSFET 비휘발성 기억소자의 Si-$SiO_2$ 계면특성에 관한 연구)

  • Kim, Hwa-Mok;Yi, Sang-Bae;Seo, Kwang-Yell;Kang, Chang-Su
    • Proceedings of the KIEE Conference
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    • 1993.07b
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    • pp.1268-1270
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    • 1993
  • In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.

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