• Journal of the Microelectronics and Packaging Society
• /
• v.8 no.4
• /
• pp.11-15
• /
• 2001

In this paper, hermetic sealing technology was studied for wafer level packaging of the RF-MEMS devices. With the flip-chip bonding method. this non-conductive B-stage epoxy sealing will be profit to the MEMS device sealing. It will be particularly profit to the RF-MEMS device sealing. B-stage epoxy can be cured by 2-step and hermetic sealing can be obtained. After defining 500 $\mu\textrm{m}$-width seal-lines on the glass cap substrate by screen printing, it was pre-baked at $90^{\circ}C$ for about 30 minutes. It was, then, aligned and bonded with device substrate followed by post-baked at $175^{\circ}C$ for about 30 minutes. By using this 2-step baking characteristic, the width and the height of the seal-line could be maintained during the sealing process. The height of the seal-line was controlled within $\pm$0.6 $\mu\textrm{m}$ in the 4 inches wafer and the bonding strength was measured to about 20MPa by pull test. The leak rate, that is sealing characteristic of the B-stage epoxy, was about $10^{-7}$ cc/sec from the leak test.

• Journal of the Microelectronics and Packaging Society
• /
• v.12 no.2 s.35
• /
• pp.105-109
• /
• 2005

A compact antenna switch module for GSM/DCS dual band applications based on multilayer low temperature co-fired ceramic (LTCC) substrate is presented. Its size is $4.5{\times}3.2{\times}0.8 mm^3$ and insertion loss is lower than 1.0 dB at Rx mode and 1.2 dB at Tx mode. To verify the stability of the developed module to the process window, each block that is diplexer, LPF's and bias circuit is measured by probing method in the variation with the thickness of ceramic layer and the correlation between each block is quantified by calculating the VSWR In the mean while, two types of bias circuits -lumped and distributed - are compared. The measurement of each block and the calculation of VSWR give good information on the behavior of full module. The reaction of diplexer to the thickness is similar to those of LPF's and bias circuit, which means good relative matching and low value of VSWR, so total insertion loss is maintained in quite wide range of the thickness of ceramic layer at both band. And lumped type bias circuit has smaller insertion itself and better correspondence with other circuit than distributed stripline structure. Evaluated ceramic module adopting lumped type bias circuit has low insertion loss and wider stability region of thickness over than 6um and this can be suitable for the mass production. Stability characterization by probing method can be applied widely to the development of ceramic modules with embedded passives in them.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.41 no.3
• /
• pp.15-20
• /
• 2004

In this paper, a wideband two-layer H-shaped microstrip antenna for WLAN is designed. To increase the bandwidth of microstrip patch antenna a configuration of stacked type using parastic element is used. Furthermore, to reduce the size of microstrip patch antenna, two techniques are employed . the first one is H-shaped patch type and the second one is that the main radiator and parastic patch are shorted to the ground plane using ten shorting posts. The antenna bandwidth and radiation characteristics are calculated by ENSEMBLE ver. 5.0 simulation software, and compared with the experimental results. Experiment results show that the bandwidth of antenna in 740MHz centered at 5.46㎓(13.5%), which is close agreement with the calculations, 770MHz(13%). Also, the antenna size can be reduced by 71.5% compared with the half wavelength rectangular microstrip antenna using the same substrate at the same frequency.

• Journal of IKEEE
• /
• v.19 no.1
• /
• pp.94-100
• /
• 2015

In this paper, 50V power U-MOSFET which replace the body(PN) diode with Schottky is proposed. As already known, Schottky diode has the advantage of reduced reverse recovery loss than PN diode. Thus, the power MOSFET with integrated Schottky integrated can minimize the reverse recovery loss. The proposed Schottky body diode U-MOSFET(SU-MOS) shows reduction of reverse recovery loss with the same transfer, output characteristic and breakdown voltage. As a result, 21.09% reduction in peak reverse current, 7.68% reduction in reverse recovery time and 35% improvement in figure of merit(FOM) are observed when the Schottky width is $0.2{\mu}m$ and the Schottky barrier height is 0.8eV compared to conventional U-MOSFET(CU-MOS). The device characteristics are analyzed through the Synopsys Sentaurus TCAD tool.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.2
• /
• pp.40-50
• /
• 2010

The studies of PMOS transistors in CMOS technologies are reviewed- focusing on the snapback and breakdown behavior of the parasitic PNP BJTs in high current regime. A new failure mechanism of PMOSFET devices under ESD conditions is also analyzed by investigating various I/O structures in a $0.13\;{\mu}m$ CMOS technology. Localized turn-on of the parasitic PNP transistor can be caused by localized charge injection from the adjacent diodes into the body of the PMOSFET, significantly degrading the ESD robustness of PMOSFETs. Based on 2-D device simulations the critical layout parameters affecting this problem are identified. Design guidelines for avoiding this new PMOSFET failure mode are also suggested.

• Journal of the Microelectronics and Packaging Society
• /
• v.6 no.4
• /
• pp.49-53
• /
• 1999

In this study, the characteristics of the structure of buried type capacitor for RF multi- chip-module are investigated. We developed many kinds of structures to minimize the space of capacitor in module and the value of parastic series inductance without any loss in capacitance, and in this procedure the effect of vias especially position, size, number length are analyzed and optimized. This characteristics of structures are checked through HFSS(high frequency structure simulator) of HP, and the value of parastic series inductance is calculated by equivalent circuit analysis. And ensuing the result of simulation, we made buried type capacitors using LTCC (low temperature cofired ceramic) material. In measurement of this sample, we found out the effective and precise method can be applied to buried type and characteristics of vias and striplines added for measuring are quantified.

• Journal of Advanced Navigation Technology
• /
• v.11 no.1
• /
• pp.72-78
• /
• 2007

In this paper, the wide-band monopole antenna with a parasitic element on the ground plane for application in Cellular, GSM and RFID mobile terminals such as the mobile phone or Personal Digital Assistant(PDA) phone is presented. The VSWR of the designed antenna is 2:1 over the frequency range of 820 MHz to 1040 MHz(bandwidth of 23.6 %). Therefore, the designed antenna can provide wide bandwidth covering the Cellular(824 MHz~894 MHz), RFID(908.5 MHz~914 MHz) and GSM(Tx:880 MHz~915 MHz, Rx:925 MHz~960 MHz). The radiation characteristics of the fabricated antenna were also studied. According to the measured radiation patterns, the maximum gains at 859 MHz and 911.25 MHz(center frequencies of the Cellualr and RFID bands) are -0.7 dBi and 0.16 dBi, respectively. The measured maximum gains of GSM bands are -0.48 dBi(897.5 MHz, the center frequency of Tx) and 1.69 dBi(942.5 MHz, the center frequency of Rx).

• Journal of Advanced Navigation Technology
• /
• v.22 no.4
• /
• pp.336-341
• /
• 2018

In this paper, we designed and implemented an ultra wideband (UWB) antenna with 5G mobile communication and WLAN bands rejection characteristics. The proposed antenna consists of a planar radiation patch with two slots, parasitic elements on both sides of the strip line and ground plane on back side. The upper n-type slot contributes for 5G mobile communication band (3.42~3.70 GHz) rejection and the lower n-type slot contributes for wireless local area network (WLAN) band (5.15~5.825 GHz) rejection. Parasitic elements were used in order to satisfy the voltage standing wave ratio (VSWR) less than or equal to 2.0 for UWB band (3.10~10.60 GHz) except two rejection bands. The Ansoft's high frequency structure simulator (HFSS) was used for antenna design and simulations. The simulated antenna showed dual rejection bands of 3.36~3.71 GHz and 5.13 ~ 5.92 GHz in UWB band, and measured result for the implemented antenna showed dual rejection bands of 3.40~3.72 GHz and 5.08~5.858 GHz. Simulated and measured VSWRs are less than or equal to 2.0 for all UWB band except dual rejection bands.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.30 no.3
• /
• pp.181-189
• /
• 2019

In this study, a triple-band antenna that can be used in WLAN(Wireless Local Area Network) at 2.4 GHz, 5.8 GHz, and 5G at 3.5 GHz is fabricated. The proposed antenna uses a parasitic element to show the triple band, and the reflector is used at a distance of ${\lambda}/4$ from the antenna to reduce the Specific Absorption Rate(SAR). Its dimensions are $100{\times}75{\times}1.6mm^3$ and each parameter value is optimized for better performance and a lower SAR value. As a result, we obtained a bandwidth of 540 MHz(2.02~2.56 GHz), 390 MHz(3.39~3.78 GHz), and 1,210 MHz(5.56~6.77 GHz) based on the reflection loss factor of -10 dB. In addition, the SAR values of the antenna with reflector are observed to reduce below the SAR value of international standard.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.9
• /
• pp.1771-1777
• /
• 2016

In this thesis, the breakdown voltage characteristics of silicon nanowire N-channel GAA MOSFETs were analyzed through experiments and 3-dimensional device simulation. GAA MOSFETs with the gate length of 250nm, the gate dielectrics thickness of 6nm and the channel width ranged from 400nm to 3.2um were used. The breakdown voltage was decreased with increasing gate voltage but it was increased at high gate voltage. The decrease of breakdown voltage with increasing channel width is believed due to the increased current gain of parasitic transistor, which was resulted from the increased potential in channel center through floating body effects. When the positive charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was decreased due to the increased potential in channel center. When the negative charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was increased due to the decreased potential in channel center. We confirmed that the measurement results were agreed with the device simulation results.