• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.56-70
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• 2010

Rendering technique generating 2 dimensional image to give reality and high performance graphical processor for efficient processing of massive data are necessary to support realistic 3 dimensional graphical image. Recently, graphical hardwares have evolved rapidly. This enables high quality rendering effect that we were unable to process in realtime. Improving shading technique enabled us to render realistic images but still much time is required for this process. Multiple operational units are being integrated in a graphical processor for effective floating point operation using massive data to process almost real looking images. In this paper, we have designed and implemented a special functional unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed special functional unit. Hardware resource usage rate and execution speed are measured implementing directly on FPGA Virtex-4(xc4vlx200).

• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.305-316
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• 2006

Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simultaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. For the above two goals, effective memory organizations including a new pixel cache architecture are presented. The experimental results show that the proposed architecture achieves almost linear speedup at best case even in sixteen rasterizers.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.4
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• pp.119-128
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• 2019

Due to the nature of the 3D graphics processor system, many mathematical calculations are required and parallel processing research using GPU (Graphics Processing Unit) is being performed for high-speed processing. In this paper, we propose a 3D graphics processor using MAMS, a parallel processor that does not use cache memory, to solve the GPU problem of increasing bandwidth caused by cache memory miss and the problem that 3D shader processing speed is not constant. The 3D graphics processor using MAMS proposed in this paper designed Vertex shader, Pixel shader, Tiling and Rasterizing structure using DirectX command analysis, the FPGA(Xilinx Virtex6@100MHz) board for MAMS was constructed and designed using Verilog. We compared the processing time of the developed FPGA (100Mhz) and nVidia GeForce GTX 660 (980Mhz), the processing time using GTX 660 was not constant and suing MAMS was constant.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.252-265
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• 2000

In this thesis, the analysis of data processing method and the amount of computation in the whole geometry processing is conducted step by step. Floating-point ALU design is based on the characteristics of geometry processing operation. The performance of the devised ALU fitting with the geometry processing operation is analyzed by simulation after the description of the proposed ALU and geometry processor. The ALU designed in the paper can perform three types of floating-point operation simultaneously-addition/subtraction, multiplication, division. As a result, the 23.5% of improvement is achieved by that floating-point ALU for the whole geometry processing and in the floating-point division and square root operation, there is another 23% of performance gain with adding area-performance efficient SRT divisor.

• Journal of the Korea Society for Simulation
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• v.30 no.1
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• pp.11-20
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• 2021

As unmanned underwater systems have recently emerged, a high-speed underwater channel modeling technique, which is one of the most important techniques in the system, has received a lot of attention. In this paper, we proposed a high-speed sound propagation model and verified the applicability through quantitative performance analyses. We used a high-order finite difference method (FDM) for wave propagation modeling in the water, and a domain decomposition method was adopted using multiple general-purpose graphics processing units (GPUs) to increase the calculation efficiency. We compared the results of the model we proposed with the analytic solution in the half-infinite media and results of the Virtual Timeseries Experiment (VirTEX) model, which is based on the ray method. Finally, we analyzed the performance of the model quantitatively using numerical examples. Through quantitative analyses of the improvement in computational performance, we confirmed that the computational speed increases linearly as the number of GPUs increases. The computation times are increased by 2 times and 8 times, respectively, when the domain size of computation and the maximum frequency are doubled. We expect that the proposed high-speed underwater channel modeling technique is able to contribute to the enhancement of national defense as an underwater communication channel model and analysis tool to develop the underwater communication technique for the unmanned underwater system.

• 전기의세계
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• v.38 no.7
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• pp.11-18
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• 1989

최근 수년간의 슈퍼컴퓨터의 성향은 확실히 변화하고 있다. 괄목할 만한 것은 초대형의 엄청난 고가의 슈퍼컴퓨터에서나 가능하였던 고해상도의 실시간 화상처리를 이제는 Desk-top 형태의 그래픽 슈퍼컴퓨터에서도 가능해졌다는 점이다. 소위 "visualization"라 불리우는 그래픽 처리를 일반화 하고 있는 것이다. 두말 할 것 없이 초고속의 저렴한 그래픽전용 프로세서의 개발과 벡터프로세싱의 구조를 적용한 초강도의 병렬성의 덕택이라 해도 과언이 아닐듯 싶다. 이렇듯 어느 한정된 응용에서의 최적화된 병렬구조가 가져다준 기술혁신은 인류문명의 찬란한 한페이지를 막 열려하고 있다 하겠다. 물론 아직도 풀리려하지 않는 근본적인 문제가 있기는 하지만 주어진 특수 분야에 국한되지 않고 어느 범용분야에도 병렬처리를 하는 궁극적인 병렬성을 수행하는 슈퍼슈퍼 컴퓨터의 제작이 가능할 것인가 하고 의문점이 생긴다. 의문점이 생긴다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2107-2115
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• 2007

In this paper, the scan conversion processor which converts the triangle represented by three vertices into pixel-level screen coordinates, depth coordinate, and color data is designed. The processor adopts scan-line algorithm which decomposes triangle into horizontal spans and then transforms the span into pixel data. By supporting top-left filling convention, it ensures that triangles that share an edge do not produce any dropouts or overlaps between adjacent polygons. It consists of about 21,400 gates and its maximum operating frequency is about 80 Mhz under 0.35um CMOS technology. Because its maximum pixel rate is about 80 Mpixels/sec, it can be applicable to mobile graphics application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.85-95
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• 2008

Characteristically, 3D graphic algorithms have to perform complex calculations on massive amount of stream data. The vertex and pixel shaders have enabled efficient execution of graphic algorithms by hardware, and these graphic processors may seem to have achieved the aim of "hardwarization of software shaders." However, the hardware shaders have hitherto been evolving within the limits of Z-buffer based algorithms. We predict that the ultimate model for future graphic processors will be an algorithm-independent integrated shader which combines the functions of both vertex and pixel shaders. We design the register file model that supports 3-dimensional computer graphic on the programmable unified shader processor. we have verified the accurate calculated value using FPGA Virtex-4(xcvlx200) made by Xilinx for operating binary files made by the implementation progress based on synthesis results.

• The Magazine of the IEIE
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• v.38 no.5
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• pp.49-55
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• 2011

• The Magazine of the IEIE
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• v.39 no.9
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• pp.28-38
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• 2012