• Proceedings of the Korea Information Processing Society Conference
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• 2000.04a
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• pp.293-298
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• 2000

최근 3차원 그래픽스 분야는 기존의 단순 이미지의 처리가 아닌 보다 나은 화질과 보다 많은 기법의 도입이 요구되어 지고 있다. 이에 본 논문에서는 가장 기본적인 실감영상의 표현 기법인 텍스쳐 매핑 기법에 대하여 논하였고, 3차원의 객체 공간에서 2차원의 스크린 공간으로의 변환으로 인해 생길 수 있는 문제점과 렌더링 알고리즘에 대해 분석하였으며, 이에 부합하는 렌더링 시스템을 설계, 분석하였다. 또한 본 시스템은 고성능 3차원 그래픽 처리를 위하여 채택되어지고 있는 프로세서-메모리 집적 방식을 이용, 래스터라이징 유닛과 프레임버퍼를 단일 칩으로 구성하여 렌더링과 텍스쳐 매핑 과정에서 발생할 수 있는 지연현상을 제거하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.1625-1628
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• 2004

본 논문은 렌더링-효과적인 삼각형 메쉬의 점진 전송을 위한 새로운 메쉬 표현 데이터 구조(점진 스트립)를 제안한다. 점진 스트립은 기간 메쉬까지 단순화된 스트립과 이러한 스트립을 단계적으로 복원할 수 있는 일련의 상세 정보로 구성된다. 점진 스트립 기반의 메쉬 전송 전송에서 메쉬 연결정보는 삼각형 스트립 상에서 직접적으로 복원되기 때문에 렌더링 과정에서 그래픽 가속기로 전송되는 데이터양을 크게 줄일 수 있다. 단순화된 스트립에서 발생하는 불필요한 과잉정보를 줄이기 위해 삼각형 스트립 표현의 간결함을 이용하여 스트립의 선축약 연산을 인코딩 하는 방법과 스트립의 정점 시퀀스를 재구성함으로써 불필요한 정점을 효과적으로 필터링하는 삼각형 스트립 필터링 알고리즘을 제안한다. 실험 결과 점진 전송동안 제안되어진 방법은 기존의 삼각형 기반 점진 전송 기법에 비해 메모리-그래픽스 프로세서 간 대역폭을 평균 40.5%~45.6% 줄인다.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.05a
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• pp.86-87
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• 2013

최근 가상화 기술에 대한 많은 관심과 연구들로 인해 가상 머신은 물리(Native) 머신에 가까운 성능을 보이며 프로세서 및 메모리 자원을 제공하고 있다. 하지만 GPU 와 같은 그래픽 하드웨어에 대한 장치 가상화는 다른 가상화 기법에 비해 연구가 미흡한 상태로 가상화 환경에서의 영상처리에 걸림돌이 되고 있다. 가상화 환경에서의 영상처리는 기존의 X 윈도우 시스템을 이용하여 영상을 처리하는데, 이는 2D 영상처리에 최적화 되어 있어서 3D 영상을 처리하는데 성능의 한계 보일 뿐만 아니라 가상 머신에서 메모리가 중복으로 복사되면서 낮은 성능 보여주고 있다. 제안하는 장치 가상화 프레임워크는 기존의 메모리의 중복 복사를 제거하면서 성능을 향상 시킬 수 있다. 본 논문에서는 가상화 환경에서 GPU 성능 향상을 위한 장치 가상화 프레임워크를 제안하고 평가를 통해 본 기법의 타당성을 입증한다.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.11a
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• pp.349-350
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• 2022

Recently, AI (Artificial Intelligence) has been applied to various technologies such as automatic driving, robot and smart communication. Currently, AI system is developed by software-based method using tensor flow, and GPU (Graphic Processing Unit) is employed for processing unit. In this work, we developed an FPGA-based (Field Programmable Gate Array) AI system , and report on image recognition system to realize the AI system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

• Journal of Engineering Education Research
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• v.6 no.1
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• pp.22-31
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• 2003

The purpose of this study was to develop CD-ROM so that students can understand 8051 Microprocessor unit easily in electronics circuit practice subject of technical high school. The study gives students, who have difficulties in learning, a chance for self-directed and supplementary learning by suggesting interface process with 8051 Practice Kit. To achieve these purposes, literature survey, collecting textbooks and materials, development of CD-ROM were gradually carried out. Each steps were as follows: Firstly, in literature survey, concepts and characteristics of multimedia and application to class were reviewed. Secondly, text contents on 8051 Microprocessor unit were analyzed, main contents were extracted and graphic, sound, animation were made. It was consisted of eight basic learning subjects, and designed to flow systematically. In this study, we presented a kind of teaching-learning material by developing CD-ROM in 8051 microprocessor unit in electronics circuit practice subject as a central matter. This material will be able to help technical high school students in learning

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.209-212
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• 2008

During several years, lots of industrial and individual products have been developed based on the text or graphic LCD module which has been gave the short developing period to the developer. With the advent of home networks and intelligent robots, the need for interaction between human and instruments has been increased. Recently, goods with a TFT-LCD come out. But in spite of a simple required performance, the complicated microprocessor, such as ARM processor, is required to interface the TFT-LCD and touch screen. Our research and development is to develope an embedded TFT-LCD module in order to use or apply to the goods through the simple interface by the general users as well as the developers. We adopt the RTOS(real time operating system) in order to operate TFT-LCD independently and various communication protocols are provided in order to offer the simple interface to users and developers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.20-25
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• 2009

We propose hardware architecture of floating-point square root and inverse square root arithmetic units using lookup tables. They are used for lighting engines and shader processor for 3D graphic processing. The architecture is based on Taylor series expansion and consists of lookup tables and correction units so that the size of look-up tables are reduced. It can be applied to 32 bit floating point formats of IEEE-754 and reduced 24 bit floating point formats. The square root and inverse square root arithmetic units for 32 bit and 24 bit floating format number are designed as the proposed architecture. They can operation in a single cycle, and satisfy the precision of $10^{-5}$ required by OpenGL 1.x ES. They are designed using Verilog-HDL and the RTL codes are verified using an FPGA.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.6
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• pp.631-636
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• 2010

With the growing trends of communication- broadcasting convergence, a hybrid IPTV that supports both IP network-based on-demand media and terrestrial or cable-based broadcast media is gaining attraction. This paper proposes a rich media framework for hybrid IPTV with support of the latest H.264 codec. For this purpose, we design and implement a media component and a RIA run-time engine customized for TV with the hybrid media. The media component has been designed to provide a uniform and efficient application interface to the various playback methods for RF broadcast and IP-based stored or live media. For performance and portability, it exploits media stream abstraction, adaptive on-demand I-frame search, and automatic calculation of play duration. Based on the proposed media interface, we develop a RIA run-time prototype. It has been carefully designed to fully utilize the built-in graphic acceleration hardware for optimized rendering in the resource-constrained IPTV environments. Demonstration and experiment results validate the performance and usefulness of the developed framework. The framework is expected to be used effectively to support graphics and hybrid media in the applications of IPTV-based VOD, advertisement, and education.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.11a
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• pp.388-389
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• 2022

Recently, AI (Artificial Intelligence) has been applied to various technologies such as automatic driving, robot and smart communication. Currently, AI system is developed by software-based method using tensor flow, and GPU (Graphic Processing Unit) is employed for processing unit. However, if software-based method employing GPU is used for AI applications, there is a problem that we can not change the internal circuit of processing unit. In this method, if high-level jobs are required for AI system, we need high-performance GPU, therefore, we have to change GPU or graphic card to perform the jobs. In this work, we developed a CNN-based FPGA (Field Programmable Gate Array) chip to solve this problem.