• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.181-182
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• 2018

본 논문에서는 전압 피드백 보상에 의한 동적 과변조 기법의 성능 향상 방법을 제안한다. 전동기 구동 시스템에서 인버터는 선형 변조 영역에서 동작할 경우 단순히 전압 이득이 1인 전압 증폭기로 볼 수 있다. 그러나 과변조 영역에서는 기존의 동적 과변조 기법 적용 시 지령 전압에 대한 인버터 출력 전압의 비선형성으로 인해 전압 이득이 1보다 작아진다. 따라서 과변조 성능이 저하되는데 본 논문에서는 제한된 전압을 피드백 보상하여 과변조 성능을 향상시켰다. 이로 인해 구동 전동기의 출력 토크 성능 및 전류 제어 동특성이 향상될 수 있다. 제안된 방법을 800W PMSM(Permanent Magnet Synchronous Motor)의 약자속 제어에 적용하여 그 효용성을 확인하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.384-390
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• 2008

Chaotic OOK modulation method can be used in LDR(Low Data Rate) UWB systems. In this paper, UWB chaotic-OOK transmitter system is designed and verified using TSMC 0.18 um CMOS process. A transmitter system is composed of Quasi-chaotic signal generator, OOK Modulator, and driving amplifier. The traditional chaotic signal generators using analog feedback method is weak to process variation. In order to solve this problem, a quasi-chaotic signal generator using digital feedback technique is get wide band signal and OOK Modulator using T-type switching structure is used to enhance the isolation characteristic. A driving amplifier has differential to single structure to avoid an external balun for low cost communication. The measured output power spectrum of the transmitter meet the FCC regulation and the result of the modulation test at data rate of 20 Kbps, 200 Kbps, 2 Mbps, and 10 Mbps is conformed to LDR UWB system. It is shown that the transmitter in this paper can be used for the UWB chaotic-OOK system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1297-1306
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• 2012

This work presents a 77 GHz radar transmitter for the automotive radar system. An integrated 13 GHz frequency synthesizer fabricated using 130 nm RF CMOS process drives a commercial W-band compound semiconductor monolithic multifunction amplifier(MPA), which includes a frequency multiplier by six to generate 77 GHz transmitting signal. The 13 GHz frequency synthesizer includes a high efficiency injection buffer of 4 dBm output power to drive the MPA. The output power of 77 GHz radar transmitter is higher than 13.99 dBm and the magnitude of the reference spur relative to the carrier is -36.45 dBc. The phase noise is -81 dBc/Hz at 1 MHz offset frequency from the carrier.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.402-403
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• 2011

This paper has proposed a $0.13-{\mu}m$ CMOS RF Front-end transmitter for LTE-Advanced systems. The proposed RF Front-end supports a band 7 (from 2500 MHz to 2570 MHz) in E-UTRA of 3GPP. It can provide a maximum output power level of +10 dBm but it's a normal output power level is +0 dBm considering a low PAPR. The post-layout simulation results show that the quadrature up-conversion mixer and a driver amplifier consumes 14 mA and 28 mA from a 1.2 V supply voltage respectively, while providing a output power level of 0 dBm at the input power level of -13 dBm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.634-639
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• 2006

In this paper an MMIC 2-stage power amplifier is designed and fabricated for 5GHz wireless LAN applications using $0.5{\mu}m$ gate length PHEMT transistors. The PHEMT gate width is optimized in order to meet the linearity and efficiency of the MMIC power amplifier. The $0.5{\mu}m\times600{\mu}m$ PHEMT for the drive stage and $0.5{\mu}m\times3000{\mu}m$ PHEMT for the amplification stage are the optimized sizes to achieve more than 25dBc of third order IMD at the power level of 3dB back-off from the input P1dB and more than 22dBm output power under a supply voltage of 3.3V. The two-stage MMIC power amplifier is designed to be used for the both of HIPERLAN/2 and IEEE 802.11a because of its broadband characteristics. The fabricated PHEMT MMIC power amplifier exhibits a 20.1dB linear power gain, a maximum 22dBm output power, a 24% power added efficiency under 3.3V supply voltage. The input and output on-chip matching circuits are included on a chip of $1400\times1200{\mu}m^2$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.11
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• pp.695-700
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• 2018

This paper presents the development of compact and lightweight broadband power amplifier module using HMIC (Hybrid Microwave Integrated Circuit) technology that could be high-density integration for many non-packaged microwave components into the small area of a high dielectric constant printed circuit board, such as a ceramic substrate, also using the special design and fabrication schemes for the structure of minimized electromagnetic interference to obtain the homogeneous electrical performance at the wideband frequency. The results confirmed that the small signal gain has a gain flatness of ${\pm}1.5dB$ within the range of 32 to 36 dB. In addition, the output power satisfied more than 30 dBm. The noise figure was measured within 7 dB, and OIP3 (Output Third Order Intercept Point) was more than 39 dBm. The fabricated broadband power amplifier satisfied the target specification required to electrically drive the high power amplifiers of jamming generators for electronic warfare, so the actual applicability to the system was verified. Future studies will be aimed at designing other similar microwave power amplifiers in the future.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1227-1234
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• 2008

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.7
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• pp.723-730
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• 2007

This paper shows how the ACLR of power amplifier can be reduced by using Anti-phase IMD linearization technique which generate anti-phase IMD in the driver stage compare to output stage's IMD. And design process proposed. From the experimental result of W-CDMA 4FA input signal, this amplifier has ACLR -55 dBc@5 MHz offset at 30 watts average power. Compare to optimum matching technique to get maximum power gain, this technique has been improved ACLR by 12 dBc. Also this amplifier meets 50 watts average output power amplifier specification in domestic market.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1816-1817
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• 2011

원자력발전소의 금속파편감시계통(LPMS : Loose Parts Monitoring System)은 원자로냉각재계통 내부에 존재할 수 있는 금속 이물질과 구조물 이완부에 의한 충격신호를 조기에 검출하여 원자로 구조물 및 핵연료 손상, 제어봉 구동장애 등을 미연에 방지하여 발전소 안전운전을 담당하는 중요 감시설비이다. LPMS는 금속 이물질이나 구조물 이완부에 의한 충격신호를 검출하기 위해 충격파에 민감한 가속도계를 원자로냉각재계통 중 금속파편이 자연적으로 모일 수 있는 각 구역의 표면에 최소 2개 이상 설치되어 있다. 원전은 규제요건에 따라 설비의 건전성 확인을 위해 24시간, 7일, 31일, 91일 마다 각 1회의 설비 건전성 시험을 수행하며, 계획예방정비기간 중에는 가속도계 주변에서 강구나 스프링 타격기를 이용한 충격시험을 통해 설비 전체의 건전성을 확인하고 있다. 설비 건전성 확인을 위해 경상운전 중에 수행하는 설비 건전성 시험에는 설비 특성상 가속도계 및 전치증폭기의 건전성을 확인할 수 없다. 따라서 본 논문에서는 경상운전 중 가속도계와 전치증폭기의 건전성을 확인할 수 있는 기법을 제시하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.522-529
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• 2002

MMIC circuits in whole receiver system was fabricated based on GaAs pHEMT technology. And a V-band downconverter module was fabricated by integrating these circuits. The downconverter module consists of a LO drive power amplifier which generates 24dBm output power, a low noise amplifier(LNA) which shows 20 dB small signal gain, an active parallel feedback oscillator which generates 1.6 dBm output power, and a cascode mixer which shows over 6dB conversion gain. The good conversion gain performance of our mixer made no need to attach any IF amplifier which grows conversion gain. Measured results of the complete downconverter show a conversion gain of over 20 dB between 57.5 GHz and 61.7GHz without IF amplifier.