• Proceedings of the Korean Environmental Sciences Society Conference
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• 2019.10a
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• pp.64-64
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• 2019

• Proceedings of the Korean Nuclear Society Conference
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• 1997.10a
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• pp.311-316
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• 1997

무붕산 노심의 부하추종운전을 위하여 출력제어기법을 개발하였다. 무붕산 노심의 출력제어 논리는 출력 준위와 제어봉의 위치에 따라 제어군의 역할을 반응도 제어에 사용되는 제어군과 출력분포 제어에 사용되는 제어군으로 구분하여 8가지의 제어군 구동 형태를 가지며, ASI 편차를 입력으로 구동할 제어군이 결정된다. 무붕산 노심의 출력제어 논리를 적용하여 ONED94 코드로 일일 부하추종운전을 모사하였다. 모사 결과 주기초(0 MWD/MTU)와 주기중(7000 MWD/MTU)에는 ASI 편차 $\pm$10% 내에서 부하추종운전이 가능하며, 85% 주기말(11000 MWD/MTU)에서는 $\pm$12% 내에서 부하추종운전이 가능한 것으로 나타났다.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.745-747
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• 2004

현재 많이 사용되는 대부분의 J2ME 프로그램은 모바일 기기의 특성상 제한된 자원을 사용하며 입력 키 등에서 발생하는 이벤트(event)들을 처리하는 이벤트-구동 프로그램이다. 이벤트-구동 프로그램에서 이벤트의 효과적인 처리는 전체 프로그램의 안전성과 신뢰성뿐만 아니라 효율에 영향을 미칠 수 있으며 보통 디버깅이 어려운 특성을 가지고 있다. 본 연구에서는 실행 중에 실시간으로 이벤트 발생 및 처리 정보를 보여줄 수 있는 모니터링 시스템을 설계 개발하였다. 이 시스템은 사용자 옵션에 따라 사용자가 관심 있는 이벤트만을 실행 중에 추적할 수 있으며 실행 후에 이벤트 관련 프로파일 정보를 제공한다. 또한 이 시스템은 코드 인라인 기법을 이용하여 실행시간 부담을 크게 줄였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.3
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• pp.222-230
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• 1998

This paper proposes a new gate drive circuit for high power IGBTs which can reduce the harmful effect of reverse recovery current at turn-on and actively suppress the overvoltage across the driven IGBT at turn-off without a snubber circuit. The turn-on scheme decreases the rising rate of the collector current by inereasing the input capacitance at turn-on transient when the gate-emitter voltage goes above threshold voltage. It results in soft transient of the reverse recovery current with no variation in turn-on delay time. The turn-off driving scheme has adaptive feature to the amplitude of collector current, so that the overvoltage can be limited much effectively at the fault collector current. Experimental results under various normal and fault conditions prove the effectiveness of the proposed circuit.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.5
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• pp.350-354
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• 2003

This study proposes a new self-driven active clamp forward converter eliminating the extra drive circuit for the active clamp switch. The converter used the auxiliary winding of the power transformer to drive the active clamp switch and a simple R-C circuit to get the dead time between the two switches. The operation principle was presented and experimental results were used to verify theoretical predictions. A 100-W (5V/20A) prototype converter built that only exhibited 1.5-turn winding number in the auxiliary winding was sufficient to drive the active clamp switch on the input of 50V. Finally, the measured efficiency of the converter was presented and the maximum efficiency of 91% was obtained.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.11
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• pp.2014-2019
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• 2006

PDP driving circuit requires switching devices and capacitors to stand up high voltages over 160V. This is the main cause that the power consumption and the cost of a PDP driving circuit increase. Conventional PDP driving circuits consist of 3 voltage sources and 16 switching devices. In this paper, we propose a PDP driving circuit using 2 voltage sources and 12 switching devices that can be operated with a lower supply voltage than conventional driving circuit. The operation of the proposed driving circuit is verified by the computer simulation. Simulation results show that the output signal can drive PDP cell when the supply voltage is higher than 45V in the input frequency range 70kHz to 100kHz.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.7 no.2
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• pp.13-18
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• 2013

In this paper design a 8 bit Current Steering D/A Converter for stimulating neuron signal. Proposed circuit in paper shows the conversion rate of 10KS/s and the power supply of 3.3V with 0.35um Magna chip CMOS process using full custom layout design. It employes segmented structure which consists of 3bit thermometer decoders and 5bit binary decoder for decreasing glitch noise and increasing resolution. So glitch energy is down by $10nV{\bullet}sec$ rather than binary weighted type DAC. And it makes use of low power current stimulator because of low LSB current. And it can make biphasic signal by connecting with Micro Controller Unit which controls period and amplitude of signal. As result of measurement INL is +0.56/-0.38 LSB and DNL is +0.3/-0.4 LSB. It shows great linearity. Power dissipation is 6mW.

• Korean Journal of Optics and Photonics
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• v.19 no.2
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• pp.132-139
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• 2008

In scanning laser optical tweezers, high speed scanning stages are used to manipulate a laser beam spot. Due to the inertia of the stage, the output scanning signal decreases with increased frequency of the input signal. This discrepancy in the signals is difficult to observe since most of the energy from the laser beam is blocked out to avoid CCD damage. In this paper, we propose two methods to alleviate these problems. Firstly, frequency responses of piezo stages are measured to analyze the signal drops and the input signal is compensated accordingly. Secondly, an overlay of the scanning path is drawn on the live monitoring screen to enhance the visibility of the scanning path. The result is a drop-compensated scanning with clear path view.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.966-967
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• 2015

본 논문은 BLDC 팬모터의 속도제어 선형성(linearity)에 관한 것이다. PWM으로 모터의 속도를 제어할 때에 입력 duty cycle이 증가함에 따라 모터 속도가 선형적으로 증가하지 않는 문제가 발생한다. 모터를 구동하는 드라이브 IC의 출력 PWM duty cycle을 속도제어의 입력값에 해당하는 입력 PWM duty cycle과 비선형적으로 출력함으로써, 모터 속도의 입력 PWM duty cycle에 대해 선형성을 향상시켰다. 또한, 비휘발성 메모리에 설정값을 저장하여 선형성 정도를 조절가능하도록 하였다. 0.35um CMOS 공정으로 단상 BLDC 모터 드라이브 IC를 설계 및 제작하고, 모터 샘플을 이용하여 PWM 입력 duty cycle과 모터 속도와의 선형성 정도를 측정하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.39-45
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• 2011

This paper proposes a low power current-steering 10-bit DAC selecting clock enable signal. The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in wihich the data will not be changed. The proposed DAC was implemented using a 0.13${\mu}m$ CMOS process with $V_{DD}=1.2V$. Its core area is 0.21$mm^2$. It consumes 4.46mW at 1MHz signal frequency and 200MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25MHz and 10MHz signal frequencies, respectively. The measured SFDRs are 72.8dB and 56.1dB at 1MHz and 50MHz signal frequencies, respectively.