• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.6
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• pp.42-48
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• 2002

The design, construction and performance test of a convenient multi-purpose irradiator is described. A multi-purpose irradiator using Cesium-137 has been developed for studies of low dose radiation effects in biology and for calibration of Thermo Luminescent dosimeter(TLD). During the operation, three rods of radioactive material which are 10cm in length revolve 180 degrees and irradiate biological samples, or TLD, and return to their shielded position, after the programmed time. A programmable Logic Controller(PLC) controls the sequence of operation, interlock, motor rotation and safety system. The rotation speed of biological samples can vary up to 20 RPM. A real time monitoring system was also incorporated to check and control the operation status of the irradiator. The capacity of the irradiation chamber was 4.5 liters. The isodose distribution at arbitrary vertical planes was measured by using film dosimetry. The dose-rate was 0.13 cGy/min in air and 0.11 cGy/min in water equivalent material in the case of Cesium-137. Range of activity was 2 Ci. The homogeneity of dose distribution in the chamber was ${\pm}$7%. The actual radiation level on the surface was within permissible levels. The irradiator had a maximum 0.35 mR/min radiation leakage on its surface.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.5 s.305
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• pp.173-180
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• 2005

In this paper, we proposed the image hiding method which decreases calculation amount by encrypt partial data using discrete wavelet transform(DWT) and linear scale quantization which were adopted as the main technique for frequency transform in JPEG2000 standard. Also we used the chaotic system and cat map which has smaller calculation amount than other encryption algorithms and then dramatically decreased calculation amount. This method operates encryption process between quantization and entropy coding for preserving compression ratio of images and uses the subband selection method. Also, suggested encryption method to JPEG2000 progressive transmission. The experiments have been performed with the Proposed methods implemented in software for about 500 images. Consequently, we are sure that the proposed is efficient image encryption methods to acquire the high encryption effect with small amount of encryption. It has been shown that there exits a relation of trade-off between the execution time and the effect of the encryption. It means that the proposed methods can be selectively used according to the application areas.

• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.4
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• pp.36-46
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• 1979

Using N_ Ch silicon gate technology . the capacitors and transistors with various dimenssion were fabricated. Although the applied process was somewhat standard the conditions of ion implantation for the gate were varied by changing the implant energies from 30keV to 60keV for B and from 100 keV to 175keV for P . The doses of the implant also changed from 3 $\times$ 10 /$\textrm{cm}^2$ to 5 $\times$ 10 /$\textrm{cm}^2$ for B and from 4$\times$ 10 /$\textrm{cm}^2$ to 7 $\times$ 10 /$\textrm{cm}^2$ for P . The D. C. parameters such as threshold voltage. substrate doping level, the degree of inversion, capacitance. flat band voltage, depletion layer width, gate oxide thickless, surface states, motile charge density, electron mobility. leakage current were evaluated and also compared with the corresponing theoretical values and / or good numbers for application. The threshold voltages measured using curve tracer and C-V plot gave good agreements with the values calculated from SUPREM II which has been developed by Stanford University process group. The threshold vol tapes with back gate bias were used to calculate the change of the substrate doping level. The measured subthreshold slope enabled the prediction of the degree of inversion The D. C. testing results suggest the realized capacitors and transistors are suited for the memory applications.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.89-96
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• 2009

As increasing the number of digital control devices installed on aircrafts and their transmission speed, various digital data buses have been introduced to provide reliable and high-speed characteristics. These characteristics of avionics data bus are highly related on the fault-tolerant performance which can make minimize jitter and loss during data transfer. In this paper, we concerned about a new traffic shaping scheme for increasing the reliability of Avionics Full Duplex Switched Ethernet (AFDX) systems based on ARINC 664 standard. We note that the conventional AFDX with a single regulator per virtual link system may produce aggregated traffics as the number of virtual links increasing. The aggregated traffic results in large jitters among frames. To remedy for the jitter and loss of data, we propose a dual regulator scheme for the AFDX system. The purpose of the additional regulator is to additionally regulate aggregated traffics from a number of per virtual link regulators. Using NS-2 simulator, we show that the proposed scheme provides a better performance than the single regulator one. It is worthwhile note that the proposed AFDX with Dual Regulator scheme can be employed to not only aircraft networks but other QoS sensitive networks for robot and industrial control systems.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.3
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• pp.11-21
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• 2010

To aim at improving performance and reflecting user's needs of retrieval, the number of researches has been actively conducted in recent year as the quantity of information and generation of the web pages exceedingly increase. One of alternative approaches can be a tagging system. It makes users be able to provide a representation of metadata including writings, pictures, and movies etc. called tag and be convenient in use of retrieval of internet resources. Tags similar to keywords play a critical role in maintaining target pages. However, they still needs time consuming labors to annotate tags, which sometimes are found to be a hinderance caused by overuse of tagging. In this paper, we present an automatic tagging scheme for a solution of current tagging system conveying drawbacks and inconveniences. To realize the approach, face recognition-based tagging system on SNS is proposed by building a face area detection procedure, linear-based classification and boosting algorithm. The proposed novel approach of tagging service can increase possibilities that utilized SNS more efficiently. Experimental results and performance analysis are shown as well.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.39-49
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• 2012

Demand for high resolution video services leads to active studies on high speed video processing. Especially, widespread deployment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. Previously proposed parallelization approach could improve the decoding performance. However, some parallelization methods did not consider the entropy decoding and others considered only a partial decoding parallelization. Therefore, we consider parallel entropy decoding integrated with other parallel video decoding process on a multi-core system. We propose a novel parallel decoding method called Integrated Parallelization. We propose a method on how to optimize the parallelization of video decoding when we have a multi-core system with many cores. We parallelized the KTA 2.7 decoder with the proposed technique on an Intel i7 Quad-Core platform with Intel Hyper-Threading technology and multi-threads scheduling. We achieved up to 70% performance improvement using IP method.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.2
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• pp.28-34
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• 2012

Various feature extraction algorithms are widely applied to real-time image processing applications for extracting significant features from images. Feature extraction algorithms are mostly combined with image processing algorithms mostly for image tracking and recognition. Feature extraction function is used to supply feature information to the other image processing algorithms and it is mainly implemented in a preprocessing stage. Nowadays, image processing applications are faced with embedded system implementation for a real-time processing. In order to satisfy this requirement, it is necessary to reduce execution time so as to improve the performance. Reducing the time for executing a feature extraction function dose not only extend the execution time for the other image processing algorithms, but it also helps satisfy a real-time requirement. This paper explains FAST (Feature from Accelerated Segment Test algorithm) of E. Rosten and presents FPGA-based embedded hardware accelerator architecture. The proposed acceleration scheme can be implemented by using approximately 2,217 Flip Flops, 5,034 LUTs, 2,833 Slices, and 18 Block RAMs in the Xilinx Vertex IV FPGA. In the Modelsim - based simulation result, the proposed hardware accelerator takes 3.06 ms to extract 954 features from a image with $640{\times}480$ pixels and this result shows the cost effectiveness of the propose scheme.

• 전자공학회논문지 IE
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• v.47 no.3
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• pp.19-25
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• 2010

We developed a RFID terminal to voice guide the blind who have difficulties in reaching out to the pharmaceutical information. In this work, we used RFID technology to instruct the pharmaceutical information to the blind. The voice guidance reader was made to read the RFID tag attached to the drugs and announced the pharmaceutical information matching to the tag specific ID. We had the reader to obtain the pharmaceutical information from the ezDrug site operated by Korea Food & Drug Association. The voice guidance reader was fabricated as necklace type for the easy carry, and we added mp3 player as dual uses. ARM series Cortex M3 chip was used for the reader's core chip and low power MFRC523 chipset of NXP was used to construct RFID circuit. MFRC523 chip uses low power to meet the mobile application. We used VS1003B MP3 Decoder IC to make the voice generation circuit and CC2500 chipset for the wireless communication to the pharmaceutical information server. We also developed the system that can support ISO 14443A type and ISO 14443B type so that the system can be used to extend to various RFID protocols. Utilization of this system can conveniently convey the pharmaceutical information to the blind and reduce the drug abuse.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.4 s.316
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• pp.28-35
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• 2007

Airbone laser altimeters have been utilized for 3D topographic mapping of the earth, moon, and planets with high resolution and accuracy, which is a rapidly growing remote sensing technique that measures the round-trip time emitted laser pulse to determine the topography. The traveling time from the laser scanner to the Earth's surface and back is directly related to the distance of the sensor to the ground. When there are several objects within the travel path of the laser pulse, the reflected laser pluses are distorted by surface variation within the footprint, generating multiple echoes because each target transforms the emitted pulse. The shapes of the received waveforms also contain important information about surface roughness, slope and reflectivity. Waveform processing algorithms parameterize and model the return signal resulting from the interaction of the transmitted laser pulse with the surface. Each of the multiple targets within the footprint can be identified. Assuming each response is gaussian, returns are modeled as a mixture gaussian distribution. Then, the parameters of the model are estimated by LMS Method or EM algorithm However, each response actually shows the skewness in the right side with the slowly decaying tail. For the application to require more accurate analysis, the tail information is to be quantified by an approach to decompose the tail. One method to handle with this problem is proposed in this study.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.20-29
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• 2014

Recently, LTE is preparing to make a new leap forward LTE-A all over the world. As LTE privides high speed service, the role of mobile phones seems to change from voice to data service. According to Cisco, global mobile data traffic will increase nearly 11-fold between 2013 and 2018. Mobile video traffic will reach 75% by 2018 from 66% in 2013 in Korea. However, voice service is still the most important role of mobile phones. Thus, controllability of throughput and low BLER is indispensable for high-quality VoIP service among various type of traffic. Although the maximum AMR-WB, 23.85 Kbps is sufficient to a VoIP call, it is difficult for the LTE which can provide tens to hundreds of MB/s may not keep the certain level VoIP QoS especially in the cell-edge area. This paper proposes a new scheduling algorithm in order to improve VoIP performance after analyzing various scheduling algorithms. The proposal is the technology which applies more priority processing for VoIP than other applications in cell-edge area based on two-tier scheduling algorithm. The simulation result shows the improvement of VoIP performance in the view point of throughput and BLER.