• Title/Summary/Keyword: 공통모드

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A Wireless Video Streaming System for TV White Space Applications (TV 유휴대역 응용을 위한 무선 영상전송 시스템)

  • Park, Hyeongyeol;Ko, Inchang;Park, Hyungchul;Shin, Hyunchol
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.4
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    • pp.381-388
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    • 2015
  • In this paper, a wireless video streaming system is designed and implemented for TV white space applications. It consists of a RF transceiver module, a digital modem, a camera, and a LCD screen. A VGA resolution video is captured by a camera, modulated by modem, and transmitted by RF transceiver module, and finally displayed at a destination 2.6-inch LCD screen. The RF transceiver is based on direct-conversion architecture. Image leakage is improved by low pass filtering LO, which successfully covers the TVWS. Also, DC offset problem is solved by current steering techniques which control common mode level at DAC output node. The output power of the transmitter and the minimum sensitivity of the receiver is +10 dBm and -82 dBm, respectively. The channel bandwidth is tunable among 6, 7 and 8 MHz according to regulations and standards. Digital modem is realized in Kintex-7 FPGA. Data rate is 9 Mbps based on QPSK and 512ch OFDM. A VGA video is successfully streamed through the air by using the developed TV white-space RF communication module.

A Study on Characteristics and Modeling of CMV by Grounding Methods of Transformer for ESS (ESS용 변압기의 접지방식에 의한 CMV 모델링 및 특성에 관한 연구)

  • Choi, Sung-Moon;Kim, Seung-Ho;Kim, Mi-Young;Rho, Dae-Seok
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.22 no.4
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    • pp.587-593
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    • 2021
  • Since 2017, a total of 29 fire accidents have occurred in energy storage systems (ESSs) as of June 2020. The common mode voltage (CMV) is one of the electrical hazards that is assumed to be a cause of those fire accidents. Several cases of CMV that violate the allowable insulation level of a battery section are being reported in actual ESS operation sites with △-Y winding connections. Thus, this paper evaluates the characteristics of CMV. An ESS site was modeled with an AC grid, PCS, and battery sections using PSCAD/EMTDC software. As a result of a simulation based on the proposed model, it was confirmed that characteristics of CMV vary significantly and are similar to actual measurements, depending on the grounding method of the internal transformer for PCS. The insulation level of the battery section may be severely degraded as the value of CMV exceeds the rated voltage in case of a grounding connection. It was found that the value of CMV dramatically declines when the internal transformer for PCS is operated as non-grounding connection, so it meets the standard insulation level.

Design of a Low-Power 8-bit 1-MS/s CMOS Asynchronous SAR ADC for Sensor Node Applications (센서 노드 응용을 위한 저전력 8비트 1MS/s CMOS 비동기 축차근사형 ADC 설계)

  • Jihun Son;Minseok Kim;Jimin Cheon
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.16 no.6
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    • pp.454-464
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    • 2023
  • This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

A Design of Secure Electronic Health Information Management Protocol in the Internet of Things Environment (사물 인터넷 환경에서 안전한 전자의료정보 관리 프로토콜 설계)

  • Park, Jeong Hyo;Kim, Nak Hyun;Jung, Yong Hoon;Jun, Moon Seog
    • KIPS Transactions on Computer and Communication Systems
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    • v.3 no.10
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    • pp.323-328
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    • 2014
  • ZigBee based on the most vulnerable part of u-Healthcare system that uses the ZigBee communication is the wireless section. ZigBee communication sectors to identify vulnerabilities in this paper, we propose to compensate. ZigBee has been raised from the existing vulnerabilities organize and ZigBee also uses the 64bit address that uniquely identifies a vulnerability that was defined as exposure. And to prevent the exposure of a unique identifying address was used to address a temporary identification. ZigBee security services, the proposed system during the Network Key for encryption only use one mechanism of Residential Mode is used. Residential Mode on all nodes of the entire network because they use a common key, the key is stolen, your network's security system at a time are at risk of collapse. Therefore, in order to guard against these risks to the security policy Network Key updated periodically depending on the method used to. The proposed evaluation and comparative analysis of the system were exposed in the existing system can hide the address that uniquely identifies a public key Network Key also updated periodically, so that leaks can occur due to reduced risk.

Design of 4th Order ΣΔ modulator employing a low power reconfigurable operational amplifier (전력절감용 재구성 연산증폭기를 사용한 4차 델타-시그마 변조기 설계)

  • Lee, Dong-Hyun;Yoon, Kwang-Sub
    • Journal of IKEEE
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    • v.22 no.4
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    • pp.1025-1030
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    • 2018
  • The proposed modulator is designed by utilizing a conventional structure employing time division technique to realize the 4th order delta-sigma modulator using one op-amp. In order to reduce the influence of KT/C noise, the capacitance in the first and second integrators reused was chosen to be 20pF and capacitance of third and fourth integrators was designed to be 1pF. The stage variable technique in the low power reconfigurable op-amp was used to solve the stability issue due to different capacitance loads for the reduction of KT/C noise. This technique enabled the proposed modulator to reduce the power consumption of 15% with respect to the conventional one. The proposed modulator was fabricated with 0.18um CMOS N-well 1 poly 6 metal process and consumes 305uW at supply voltage of 1.8V. The measurement results demonstrated that SNDR, ENOB, DR, FoM(Walden), and FoM(Schreier) were 66.3 dB, 10.6 bits, 83 dB, 98 pJ/step, and 142.8 dB at the sampling frequency of 256kHz, oversampling ratio of 128, clock frequency of 1.024 MHz, and input frequency of 250 Hz, respectively.

Transcoding Algorithm for AMR and EVRC Vocoders Via Direct Parameter Transformation (AMR과 EVRC 음성부호화기를 위한 파라미터 직접 변환 방식의 상호부호화 알고리듬)

  • Lee, Sun-Il;Yu, Chang-Dong
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.39 no.6
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    • pp.696-708
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    • 2002
  • In this paper, a novel transcoding algorithm for the Adaptive Multi Rate(AMR) and the Enhanced Variable Rate Codec(EVRC) vocoders via direct parameter transformation is proposed. In contrast to the conventional tandem transcoding algorithm, the proposed algorithm converts the parameters of one coder to the other without going through the decoding and encoding processes. The proposed algorithm consists of the parameter decoding, frame classification, mode decision, and transcoders for two frame types. The transcoders convert the parameters such as LSP, frame energy, pitch delay for the adaptive codebook, fixed codebook vector, and codebook gains. Evaluation results show that while exhibiting better computational and delay characteristics, the proposed algorithm produces equivalent speech quality to that produced by the tandem transcoding algorithm.

Quality Assessment of Hatchway Using QFD & FMEA (QFD와 FMEA를 이용한 화물창구의 품질 평가)

  • Seung-Min Kwon;Young-Soon Yang;Chan-Ho Shin
    • Journal of the Society of Naval Architects of Korea
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    • v.37 no.3
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    • pp.78-89
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    • 2000
  • The quality of a product/system is getting more important concept nowadays. 'Performance', as one of the quality characteristics, means how well a product carries out its given functions and is the most adjacent characteristics to the customer satisfaction. To an engineer, however, who deals with large structures such as ships, 'Safety' is actually getting more important because of its direct relationship with failures of a product/system itself and human injuries when an accident occurs. In this study, therefore, we consider both performance and safety recognized the most important elements in dealing with structures and present a quality analysis method based on customer requirements by using QFD for performance analysis and FMEA for safety analysis respectively. Applying these methods to the hatchway of a bulk carrier, we could find 8 and 12 important parts based on performance and safety respectively. Among these, only 7 parts were pointed out commonly critical. From these, we can suggest that designers should pay more attention to these 7 parts and thus give a high priority of concerns to them when trying to improve the quality of system.

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Design of 24-GHz Power Amplifier for Automotive Collision Avoidance Radars (차량 추돌 방지 레이더용 24-GHz 전력 증폭기 설계)

  • Noh, Seok-Ho;Ryu, Jee-Youl
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.1
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    • pp.117-122
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    • 2016
  • In this paper, we propose 24-GHz CMOS radio frequency (RF) power amplifier for short-range automotive collision avoidance radars. This circuit contains common source stage with inter-stages conjugate matching circuit as a class-A mode amplifier. The proposed circuit is designed using TSMC $0.13-{\mu}m$ mixed signal/RF CMOS process ($f_T/f_{MAX}=120/140GHz$). It operates at the supply voltage of 2V, and it is designed to have high power gain, low insertion loss and low noise figure in the low supply voltage. To reduce total chip area, the circuit used transmission lines instead of the bulky real inductor. The designed CMOS power amplifier showed the smallest chip size of $0.1mm^2$, the lowest power consumption of 40mW, the highest power gain of 26.5dB, the highest saturated output power of 19.2dBm and the highest maximum power-added efficiency of 17.2% as compared to recently reported results.

Development of Mobile Volume Visualization System (모바일 볼륨 가시화 시스템 개발)

  • Park, Sang-Hun;Kim, Won-Tae;Ihm, In-Sung
    • Journal of KIISE:Computing Practices and Letters
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    • v.12 no.5
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    • pp.286-299
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    • 2006
  • Due to the continuing technical progress in the capabilities of modeling, simulation, and sensor devices, huge volume data with very high resolution are common. In scientific visualization, various interactive real-time techniques on high performance parallel computers to effectively render such large scale volume data sets have been proposed. In this paper, we present a mobile volume visualization system that consists of mobile clients, gateways, and parallel rendering servers. The mobile clients allow to explore the regions of interests adaptively in higher resolution level as well as specify rendering / viewing parameters interactively which are sent to parallel rendering server. The gateways play a role in managing requests / responses between mobile clients and parallel rendering servers for stable services. The parallel rendering servers visualize the specified sub-volume with rendering contexts from clients and then transfer the high quality final images back. This proposed system lets multi-users with PDA simultaneously share commonly interesting parts of huge volume, rendering contexts, and final images through CSCW(Computer Supported Cooperative Work) mode.

Design of Small-Area and High-Reliability 512-Bit EEPROM IP for UHF RFID Tag Chips (UHF RFID Tag Chip용 저면적·고신뢰성 512bit EEPROM IP 설계)

  • Lee, Dong-Hoon;Jin, Liyan;Jang, Ji-Hye;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.2
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    • pp.302-312
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    • 2012
  • In this paper, small-area and high-reliability design techniques of a 512-bit EEPROM are designed for UHF RFID tag chips. For a small-area technique, there are a WL driver circuit simplifying its decoding logic and a VREF generator using a resistor divider instead of a BGR. The layout size of the designed 512-bit EEPROM IP with MagnaChip's $0.18{\mu}m$ EEPROM is $59.465{\mu}m{\times}366.76{\mu}m$ which is 16.7% smaller than the conventional counterpart. Also, we solve a problem of breaking 5V devices by keeping VDDP voltage constant since a boosted output from a DC-DC converter is made discharge to the common ground VSS instead of VDDP (=3.15V) in getting out of the write mode.