• Title/Summary/Keyword: 공정열

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Synthesis and Characterization of Titania-Partially-Stabilized Zirconia by Ultrasonic Spray Pyrolysis (초음파분무열분해법에 의한 TPSZ의 합성 및 특성)

  • Seo, Ki-Lyong;Ri, Chang-Seop
    • Journal of the Korean Chemical Society
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    • v.44 no.6
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    • pp.592-599
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    • 2000
  • The fine particles of binary ceramic composite of titania-partially-stabilized zirconia(TPSZ) were synthesized by ultrasonic spray pyrolysis at the various temperatures, compositions and concentrations and the effects of process factors for synthesis on the characteristics of fine particles were discussed. The starting salt solutions were prepared to have the ionic concentrations of 0.025~0.1 M aqueous solutions. The fine particles were prepared to have the compositions of 90~97.5 wt% of $ZrO_2$ and 2.5~10 wt% of $TiO_2$. The temperatures for particle synthesis were regulated to be 400~550$^{\circ}C$ as a drying zone, 800~1100$^{\circ}C$ as a pyrolysis zone. The produced fine particles were collected by a wet process and analyzed to investigate characteristic properties after being dried. The compositions of ceramic fine particles were determined by Inductively Coupled Plasma-Atomic Emission Spectroscopy(ICP-AES) technique and phases, morphologies and particle sizes of those were investigated by Raman Spectroscopy, X-ray diffraction(XRD), Scanning Electron Microscopy(SEM), Transmission Electron Microscopy(TEM) and Particle Size Analyzer(PSA) techniques.

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The Effect of the Core-shell Structured Meta-aramid/Epoxy Nanofiber Mats on Interfacial Bonding Strength with an Epoxy Adhesive in Cryogenic Environments (극저온 환경에서 에폭시 접착제의 물성 향상을 위한 나노 보강재의 표면 개질에 관한 연구)

  • Oh, Hyun Ju;Kim, Seong Su
    • Composites Research
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    • v.26 no.2
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    • pp.129-134
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    • 2013
  • The strength of adhesive joints employed in composite structures under cryogenic environments, such as LNG tanks, is affected by thermal residual stress generated from the large temperature difference between the bonding process and the operating temperature. Aramid fibers are noted for their low coefficient of thermal expansion (CTE) and have been used to control the CTE of thermosetting resins. However, aramid composites exhibit poor adhesion between the fibers and the resin because the aramid fibers are chemically inert and contain insufficient functional groups. In this work, electrospun meta-aramid nanofiber-reinforced epoxy adhesive was fabricated to improve the interfacial bonding between the adhesive and the fibers under cryogenic temperatures. The CTE of the nanofiber-reinforced adhesives were measured, and the effect on the adhesion strength was investigated at single-lap joints under cryogenic temperatures. The fracture toughness of the adhesive joints was measured using a Double Cantilever Beam (DCB) test.

Effects of Metallic Silicon on the Synthsis of β-SiC Powders by a Carbothermal Reduction Using SiO2-C Hybrid Precursor Fabricated by a Sol-gel Process (솔-젤 공정으로 제조된 SiO2-C 복합 전구체를 사용하여 열탄소환원법에 의한 β-SiC 분말 합성에 금속 Si 첨가가 미치는 영향)

  • Jo, Yung-Chul;Youm, Mi-Rae;Yun, Sung-Il;Cho, Gyoung-Sun;Park, Sang-Whan
    • Journal of the Korean Ceramic Society
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    • v.50 no.6
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    • pp.402-409
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    • 2013
  • The objective of this study was to develop a synthesis process for ${\beta}$-SiC powders to reduce the synthesis temperature and to control the particle size and to prevent particle agglomeration of the synthesized ${\beta}$-SiC powders. A phenol resin and TEOS were used as the starting materials for the carbon and Si sources, respectively. $SiO_2$-C hybrid precursors with various C/Si mole ratios were fabricated using a conventional sol-gel process. ${\beta}$-SiC powders were synthesized by a carbothermal reduction process using $SiO_2$-C hybrid precursors with various C/Si mole ratios (1.6 ~ 2.5) fabricated using a sol-gel process. In this study, the effects of excess carbon and the addition of Si powders to the $SiO_2$-C hybrid precursor on the synthesis temperature and particle size of ${\beta}$-SiC were examined. It was found that the addition of metallic Si powders to the $SiO_2$/C hybrid precursor with excess carbon reduced the synthesis temperature of the ${\beta}$-SiC powders to as low as $1300^{\circ}C$. The synthesis temperature for ${\beta}$-SiC appeared to be reduced with an increase of the C/Si mole ratio in the $SiO_2$-C hybrid precursor by a direct carburization reaction between Si and excess carbon.

Design of Nonlinear Model Using Type-2 Fuzzy Logic System by Means of C-Means Clustering (C-Means 클러스터링 기반의 Type-2 퍼지 논리 시스템을 이용한 비선형 모델 설계)

  • Baek, Jin-Yeol;Lee, Young-Il;Oh, Sung-Kwun
    • Journal of the Korean Institute of Intelligent Systems
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    • v.18 no.6
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    • pp.842-848
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    • 2008
  • This paper deal with uncertainty problem by using Type-2 fuzzy logic set for nonlinear system modeling. We design Type-2 fuzzy logic system in which the antecedent and the consequent part of rules are given as Type-2 fuzzy set and also analyze the performance of the ensuing nonlinear model with uncertainty. Here, the apexes of the antecedent membership functions of rules are decided by C-means clustering algorithm and the apexes of the consequent membership functions of rules are learned by using back-propagation based on gradient decent method. Also, the parameters related to the fuzzy model are optimized by means of particle swarm optimization. The proposed model is demonstrated with the aid of two representative numerical examples, such as mathematical synthetic data set and Mackey-Glass time series data set and also we discuss the approximation as well as generalization abilities for the model.

Application of Insulation Curing Method with Double Bubble Sheets Subjected to Cold Weather (이중 버블시트를 이용한 단열양생공법의 한중시공 적용 사례)

  • Hong, Seak-Min;Lee, Chung-Sub;Kim, Jong;Jeon, Chung-Kun;Han, Min-Cheol;Han, Cheon-Goo
    • Proceedings of the Korea Concrete Institute Conference
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    • 2008.04a
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    • pp.1001-1004
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    • 2008
  • This study reviewed the results of utilization of insulation heat curing method using double layer bubble sheet in slab concrete and mass concrete in cold weather environment. First of all, when double layer bubble sheets are applied, it was shown that slab concrete was protected from early freezing by remaining between 6 and $10^{\circ}C$ even in case outside temperature drops $10^{\circ}C$ below zero until the 2nd day from piling, and in the case of mass concrete, with the maximum temperature difference between the center and surface less than $6^{\circ}C$, crack occurrence index was close to 2 and no hydration heat crack occurred by internal constraint. The insulation heat preservation curing method using the double bubble sheet applied in this field prevented early freezing owing to stable curing temperature management, deterring concrete strength development delay at low temperature, and obtained the needed strength. Also, it was proven that the method is highly effective and economic for cold weather concrete quality maintenance through curing cost reduction like construction period shortening and labor cost reduction, etc by reducing the process of temporary equipment installation and disassembling.

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Design of a Logic eFuse OTP Memory IP (Logic eFuse OTP 메모리 IP 설계)

  • Ren, Yongxu;Ha, Pan-bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.2
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    • pp.317-326
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    • 2016
  • In this paper, a logic eFuse (electrical Fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) using only logic transistors to reduce the development cost and period of OTP memory IPs is designed. To secure the reliability of other IPs than the OTP memory IP, a higher voltage of 2,4V than VDD (=1.5V) is supplied to only eFuse links of eFuse OTP memory cells directly through an external pad FSOURCE coming from test equipment in testing wafers. Also, an eFuse OTP memory cell of which power is supplied through FSOURCE and hence the program power is increased in a two-dimensional memory array of 128 rows by 8 columns being also able to make the decoding logic implemented in small area. The layout size of the designed 1kb eFuse OTP memory IP with the Dongbu HiTek's 110nm CIS process is $295.595{\mu}m{\times}455.873{\mu}m$ ($=0.134mm^2$).

Design of a Triple-input Energy Harvesting Circuit with MPPT Control (MPPT 제어기능을 갖는 삼중입력 에너지 하베스팅 회로 설계)

  • Yoon, Eun-Jung;Park, Jong-Tae;Yu, Chong-Gun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.346-349
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    • 2013
  • This paper describes a triple-input energy harvesting circuit using solar, vibration and thermoelectric energy with MPPT(Maximum Power Point Tracking) control. The designed circuit employs MPPT control to harvest maximum power available from a solar cell, PZT vibration element and thermoelectric generator. The harvested energies are simultaneously combined and stored in a storage capacitor, and then managed and transferred into a sensor node by PMU(Power Management Unit). MPPT controls are implemented using the linear relation between the open-circuit voltage of an energy transducer and its MPP(Maximum Power Point) voltage. The proposed circuit is designed in a CMOS 0.18um technology and its functionality has been verified through extensive simulations. The designed chip occupies $945{\mu}m{\times}995{\mu}m$.

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A Low-Power MPPT Interface for DC-Type Energy Harvesting Sources (DC 유형의 에너지 하베스팅 자원을 활용한 저전력의 MPPT 인터페이스)

  • Jo, Woo-Bin;Lee, Jin-Hee;Yu, Chong-Gun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2018.10a
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    • pp.35-38
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    • 2018
  • This paper describes a low-power MPPT interface for DC-type energy harvesting sources. The proposed circuit consists of an MPPT controller, a bias generator, and a voltage detector. The MPPT controller consists of an MPG (MPPT Pulse Generator) with a schmitt trigger, a logic gate operating according to energy type (light, heat), and a sample/hold circuit. The bias generator is designed by employing a beta multiplier structure, and the voltage detector is implemented using a bulk-driven comparator and a two-stage buffer. The proposed circuit is designed with $0.35{\mu}m$ CMOS process. The simulation results show that the designed circuit consumes less than 100nA of current at an input voltage of less than 3V and the maximum power efficiency is 99.7%. The chip area of the designed circuit is $1151{\mu}m{\times}940{\mu}m$.

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Adsorption Kinetics and Thermodynamics of Brilliant Blue FCF Dye onto Coconut Shell Based Activated Carbon (야자계 활성탄에 의한 Brilliant Blue FCF 염료의 흡착 동력학 및 열역학에 관한 연구)

  • Lee, Jong Jib
    • Korean Chemical Engineering Research
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    • v.53 no.3
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    • pp.309-314
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    • 2015
  • Adsorption of brilliant blue FCF dye from aqueous solution using coconut shell based activated carbon was investigated. Batch experiments were carried out as function of adsorbent dose, initial concentration, contact time and temperature. The equilibrium adsorption data were analyzed by Langmuir and Freundlich model. The results indicate that Freundlich model provides the best correlation of the experimental data. Base on the estimated Freundlich constant (1/n=0.129~0.212), this process could be employed as effective treatment method. Adsorption kinetics experimental data were modeled using the pseudo-first-order and pseudo-second-order kinetic equation. It was shown that pseudo-second-order kinetic equation could best describe the adsorption kinetics. Base on the negative Gibbs free energy value (-4.81~-10.33 kJ/mol) and positive enthalpy value (+78.59 kJ/mol) indicate that the adsorption is spontaneous and endothermic process.

Design of digital clock level translator with 50% duty ratio from small sinusoidal input (작은 정현파입력의 50% Duty Ratio 디지털 클럭레벨 변환기 설계)

  • Park, Mun-Yang;Lee, Jong-Ryul;Kim, Ook;Song, Won-Chul;Kim, Kyung-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.8
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    • pp.2064-2071
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    • 1998
  • A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

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