• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.6
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• pp.125-134
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• 2004

When cryptosystem designers implement devices that computing power or memory is limited such as smart cards, PDAs and so on, not only he/she has to be careful side channel attacks(SCA) but also the cryptographic algorithms within the device has to be efficient using small memory. For this purpose, countermeasures such as Moiler's method, Okeya-Takagi's one and overlapping window method, based on window method to prevent SCA were proposed. However, Moiler's method and Okeya-Talngi's one require additional cost to prevent other SCA such as DPA, Second-Order DPA, Address-DPA, and so on since they are immune to only SPA. Also, overlapping window method has a drawback that requires big memory. In this paper, we analyze existing countermeasures and propose an efficient and secure countermeasure that is immune to all existing SCA using advantages of each countermeasure. Moreover, the proposed countermeasure can enhance the efficiency using mixed coordinate systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1868-1873
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• 2021

This paper proposes the Hough transform(HT) using an extended lookup table(LUT) to reduce the computational burden of the HT that is a typical straight line detection algorithm, and analyzes its performance. The conventional HT also uses a LUT to the calculation of the parameter 𝜌 of all straight lines passing through an edge pixel of interest(ePel) in order to reduce the computational burden. However, the proposed HT adopts an extended LUT that can be applied to straight lines across the ePel as well as its peripheral edge pixels to induce more computational reduction. This paper proves the validity of the proposed algorithm mathematically and also verifies it through simulation. The simulation results show that the proposed HT reduces the multiplication computation from 49.6% up to 16.1%, depending on the image and the applied extended LUT, compared to the conventional HT.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.94-104
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• 2008

In this paper, we propose a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator which has the largest delay in MAC was removed and its function was included into CSA, the overall performance becomes to be elevated. The proposed CSA tree uses 1's complement-based radix-2 modified booth algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of operands. The CSA propagates the carries by the least significant bits of the partial products and generates the least significant bits in advance for decreasing the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits not the output of the final adder for improving the performance by optimizing the efficiency of pipeline scheme. The proposed architecture was synthesized with $250{\mu}m,\;180{\mu}m,\;130{\mu}m$ and 90nm standard CMOS library after designing it. We analyzed the results such as hardware resource, delay, and pipeline which are based on the theoretical and experimental estimation. We used Sakurai's alpha power low for the delay modeling. The proposed MAC has the superior properties to the standard design in many ways and its performance is twice as much than the previous research in the similar clock frequency.

• Journal of Elementary Mathematics Education in Korea
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• v.20 no.1
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• pp.105-129
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• 2016

The elements of mathematical processes include mathematical reasoning, mathematical problem-solving, and mathematical communications. Proportion reasoning is a kind of mathematical reasoning which is closely related to the ratio and percent concepts. Proportion reasoning is the essence of primary mathematics, and a basic mathematical concept required for the following more-complicated concepts. Therefore, the study aims to analyze the proportion reasoning ability of sixth graders of primary school who have already learned the ratio and percent concepts. To allow teachers to quickly recognize and help students who have difficulty solving a proportion reasoning problem, this study analyzed the characteristics and patterns of proportion reasoning of sixth graders of primary school. The purpose of this study is to provide implications for learning and teaching of future proportion reasoning of higher levels. In order to solve these study tasks, proportion reasoning problems were developed, and a total of 22 sixth graders of primary school were asked to solve these questions for a total of twice, once before and after they learned the ratio and percent concepts included in the 2009 revised mathematical curricula. Students' strategies and levels of proportional reasoning were analyzed by setting up the four different sections and classifying and analyzing the patterns of correct and wrong answers to the questions of each section. The results are followings; First, the 6th graders of primary school were able to utilize various proportion reasoning strategies depending on the conditions and patterns of mathematical assignments given to them. Second, most of the sixth graders of primary school remained at three levels of multiplicative reasoning. The most frequently adopted strategies by these sixth graders were the fraction strategy, the between-comparison strategy, and the within-comparison strategy. Third, the sixth graders of primary school often showed difficulty doing relative comparison. Fourth, the sixth graders of primary school placed the greatest concentration on the numbers given in the mathematical questions.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.21-34
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• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.815-823
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• 1993

In this paper, the structure of modified multiplication-free adaptive filter(M-MADF) and convergence analysis are presented. To evaluate the performance of proposed M-MADF algorithm, fractionally spaced equalizer (FSE) is used. The input signals are quantized using DPCM and the reference signals is processed using a first-order linear prediction filter, and the outputs are processed by a conventional adaptive filter. The filter coefficients are updated using the Sign algorithm. Under the assumption that the primary and reference signals are zero mean, wide-sense stationary and Gaussian, theoretical results for the coefficient misalignment vector and its autocorrelation matrix of the filter are driven. The convergence properties of Sign. MADF and M-MADF algorithm for updating of the coefficients of a digital filter of the fractionally spaced equalizer (FSE) are investigated and compared with one another. The convergence properties are characterized by the steady state error and the convergence speed. It is shown that the convergence speed of M-MADF is almost same as Sign algorithm and is faster that MADF in the condition of same steady error. Especially it is very useful for high correlated signals.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.115-124
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• 2004

This paper proposes a high efficient and low power FIR filter chip for partial-response maximum likelihood (PRML) disk drive read channels; it is a 6-bit, 8-tap digital FIR filter. The proposed filter employs a parallel processing architecture and consists of 4 pipeline stages. It uses the modified Booth algorithm for multiplication and compressor logic for addition. CMOS pass-transistor logic is used for low power consumption and single-rail logic is used to reduce the chip area. The proposed filter is actually implemented and the chip dissipates 120mV at 100MHz, uses a 3.3V power supply and occupies 1.88 ${\times}$ 1.38 $\textrm{mm}^2$. The implemented filter requires approximately 11.7% less power compared with the existing architectures that use the similar technology.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.4
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• pp.727-738
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• 2015

Until recently, power analysis is one of the most popular research issues among various side channel analyses. Since Differential Power Analysis had been first proposed by Kocher et al., various practical power analyses correspond with software/hardware cryptographic devices have been proposed. In this paper, we analyze vulnerability of countermeasure against power analysis exploiting single power trace of public cryptographic algorithm. In ICICS 2010, Clavier et al. proposed Horizontal Correlation Analysis which can recover secret information from a single exponentiation trace and corresponding countermeasures. "Blind operands in LIM", one of their countermeasures, exploits additive blinding in order to prevent leakage of intermediate value related to secret information. However, this countermeasure has vulnerability of having power leakage that is dependant with the message known by an adversary. In this paper, we analyzed vulnerabilities by three attack scenarios and proved them by practical correlation power analysis experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.31-37
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• 2009

This paper presents an efficient frame synchronization strategy with the identification of modulation type for Digital Video Broadcasting-Satellite second generation (DVB-S2). To detect the Start Of Frame (SOF) and identify a modulation mode at low SNR, we propose a new correlator structure and a low complexity Automatic Gain Controller (AGC). The proposed frame synchronization architecture can reduce about 93% multipliers and 89% adders compared with the direct implementation of the Differential - Generalized Post Detection Integration (D-GPDI) algorithm which is very complex and the proposed a low complexity AGC consists of only 5 multipliers and 3 adders. The proposed architecture has been thoroughly verified on the Xilinx Virtex II FPGA board.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.34-42
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• 2014

This paper presents a low-complexity and high-throughput symbol detector for two-spatial-stream multiple-input multiple-output systems based on the modified maximum-likelihood symbol detection algorithm. In the proposed symbol detector, the cost function is calculated incrementally employing a multi-cycle architecture so as to eliminate the complex multiplications for each symbol, and the slicing operations are performed hierarchically according to the range of constellation points by a pipelined architecture. The proposed architecture exhibits low hardware complexity while supporting complicated modulations such as 256 QAM. In addition, various modulations and antenna configurations are supported flexibly by reconfiguring the pipeline for the slicing operation. The proposed symbol detector is implemented with 38.7K logic gates in a $0.11-{\mu}m$ CMOS process and its throughput is 166 Mbps for $2{\times}$3 16-QAM and 80Mbps for $2{\times}3$ 64-QAM where the operating frequency is 478 MHz.