• Journal of KIISE:Computer Systems and Theory
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• v.28 no.6
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• pp.289-300
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• 2001

본 논문에서는 유한 필드 GF(2$_{m}$ ) 상에서 모듈러 곱셈 A($\chi$)B($\chi$) mod P($\chi$)을 수행하는 새로운 선형 문제-크기(full-size) 시스톨릭 어레이 구조인 LSB-first 곱셈기를 제안한다. 피연산자 B($\chi$)의 LSB(least significant bit)를 먼저 사용하는 LSB-first 모듈러 곱셈 알고리즘으로부터 새로운 비트별 순환 방정식을 구한다. 데이터의 흐름이 규칙적인 순환 방정식을 공간-시간 변환으로 새로운 시스톨릭 곱셈기를 설계하고 분석한다. 기존의 곱셈기와 비교할 때 제안한 곱셈기의 면적-시간 성능이 각각 10%와 18% 향상됨을 보여준다. 또한 같은 설계방법으로 곱셈과 제곱연산을 동시에 수행하는 새로운 시스톨릭 곱셈/제곱기를 제안한다. 유한 필드상의 지수연산을 위해서 제안한 시스톨릭 곱셈/제곱기를 사용할 때 곱셈기만을 사용 할 때보다 면적-시간 성능이 약 26% 향상됨을 보여준다.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1997.11a
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• pp.221-231
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• 1997

본 논문에서는 고속 멱승을 위한 모듈라 곱셈기를 시스토릭 어레이로 설계한다. Montgomery 알고리듬 및 시스토릭 어레이 구조를 분석하고 공통 피승수 곱셈 개념을 사용한 변형된 Montgomery 알고리듬에 대해 시스토릭 어레이 곱셈기를 설계한다. 제안 곱셈기는 각 처리기 내부 연산을 병렬화 할 수 있고 연산 자체도 간단화 할 수 있어 시스토릭 어레이 하드웨어 구현에 유리하며 기존의 곱셈기를 사용하는 것보다 멱승 전체의 계산을 약 0.4배내지 0.6배로 감소시킬 수 있다.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.1003-1006
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• 2004

본 논문에서는 몽고메리 모듈러 곱셈(Montgomery Modular Multiplication) 알고리즘을 이용하여 효율적인 모듈러 곱셈기를 제안한다. 본 논문에서 제안한 곱셈기는 프로그램 가능한 셀룰라 오토마타(Programmable Cellular Automata, PCA)를 기반의 구조로 설계되어 하드웨어 복잡도를 줄이고, 곱셈시 몽고메리 알고리즘을 이용하여 일반적인 나눗셈 없이 모듈러 연산을 수행하여 시간 복잡도를 최소화 한다. 제안된 곱셈기는 시간적, 공간적인 면에서 간단하고 효과적으로 구성되어 지수연산을 위한 하드웨어의 하부구조나 오류 수정 코드(Error Correcting Code)의 연산에서 효율적으로 이용될 수 있을 것이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.36-42
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• 2009

This paper proposes the high-performance pipeline architecture for modified Booth multipliers. The proposed multiplier circuits are based on modified Booth algorithm and pipeline architecture which are the most widely used techniques to accelerate the multiplication speed. In order to implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The experimental results show that the speed improvement gain exceeds the area penalty and this trend is manifested as the number of pipeline stages increases. It is also important to insert the pipeline registers at the proper positions. We described the proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits using 0.13um standard cell library. The resultant multiplier circuits show better performance than others. Since they operate at GHz ranges, they can be used in the application systems requiring extremely high performance such as optical communication systems.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.143-150
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• 2005

This paper proposes a new $radix-2^4$ FFT algorithm and an efficient pipeline architecture based on this new algorithm for OFDM systems. The pipeline architecture based on the new algorithm has the same number of multipliers as that of the $radix-2^2$ algorithm. However, the multiplier complexity could be reduced by more than $30\%$ by replacing one half of the programmable complex multipliers by the newly proposed CSD constant complex multipliers. From synthesis simulations of a standard 0.35um CMOS Samsung process, a proposed CSD constant complex multiplier achieved more than $60\%$ area efficiency when compared with the conventional programmable complex multiplier. This promoted efficiency can be used for the design of a long length FFT processor in wireless OFDM applications which needs more power and area efficiency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.5
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• pp.17-30
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• 2001

In this paper, we implemented a scalar multiplier needed at an elliptic curve cryptosystem over standard basis in $GF(2^{163})$. The scalar multiplier consists of a radix-16 finite field serial multiplier and a finite field inverter with some control logics. The main contribution is to develop a new fast finite field inverter, which made it possible to avoid time consuming iterations of finite field multiplication. We used an algorithmic transformation technique to obtain a data-independent computational structure of the Extended Euclid GCD algorithm. The finite field multiplier and inverter shown in this paper have regular structure so that they can be easily extended to larger word size. Moreover they can achieve 100% throughput using the pipelining. Our new scalar multiplier is synthesized using Hyundai Electronics 0.6$\mu\textrm{m}$ CMOS library, and maximum operating frequency is estimated about 140MHz. The resulting data processing performance is 64Kbps, that is it takes 2.53ms to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption & decryption and key exchange in real time embedded-processor environments.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.1_2
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• pp.62-68
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• 2006

The important arithmetic operations over finite fields include multiplication and exponentiation. An exponentiation operation can be implemented using a series of squaring and multiplication operations over GF($2^m$) using the binary method. Hence, it is important to develop a fast algorithm and efficient hardware for multiplication. This paper presents an efficient bit-serial systolic array for MSB-first multiplication in GF($2^m$) based on the polynomial representation. As compared to the related multipliers, the proposed systolic multiplier gains advantages in terms of input-pin and area-time complexity. Furthermore, it has regularity, modularity, and unidirectional data flow, and thus is well suited to VLSI implementation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.4
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• pp.97-102
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• 2007

In this paper, a new architecture for fast-serial $GF(2^m)$ multiplier with low hardware complexity is proposed. The fast-serial multiplier operates standard basis of $GF(2^m)$ and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the fast-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But The traditional fast-serial architecture needs extra (t-1)m registers for achieving the t times speed. In this paper a new fast-serial multiplier without increasing the number of registers is presented.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.3
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• pp.45-50
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• 2008

The choice of an irreducible polynomial and the representation of elements have influence on the efficiency of operators for finite fields. This paper suggests two serial multiplier for the extention field GF$(p^n)$ where p is odd prime. A serial multiplier using an irreducible binomial consists of (2n+5) resisters, 2 MUXs, 2 multipliers of GF(p), and 1 adder of GF(p). It obtains the mulitplication result after $n^2+n$ clock cycles. A serial multiplier using an AOP consists of (2n+5) resisters, 1 MUX, 1 multiplier of CF(p), and 1 adder of GF(p). It obtains the mulitplication result after $n^2$+3n+2 clock cycles.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.2
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• pp.105-111
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• 2006

Cryptographic application and coding theory require operations in finite field $GF(2^m)$. In such a field, the area and time complexity of implementation estimate by memory and time delay. Therefore, the effort for constructing an efficient multiplier in finite field have been proceeded. Massey-Omura proposed a multiplier that uses normal bases to represent elements $CH(2^m)$ [11] and Agnew at al. suggested a sequential multiplier that is a modification of Massey-Omura's structure for reducing the path delay. Recently, Rayhani-Masoleh and Hasan and S.Kwon at al. suggested a area efficient multipliers for modifying Agnew's structure respectively[2,3]. In [2] Rayhani-Masoleh and Hasan proposed a modified multiplier that has slightly increased a critical path delay from Agnew at al's structure. But, In [3] S.Kwon at al. proposed a modified multiplier that has no loss of a time efficiency from Agnew's structure. In this paper we will propose a multiplier by modifying Rayhani-Masoleh and Hassan's structure and the area-time complexity of the proposed multiplier is exactly same as that of S.Kwon at al's structure for type-II optimal normal basis.