• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.3 s.345
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• pp.59-67
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• 2006

OFDM (Orthogonal frequency Division Multiplexing) systems convert serial data stream to N parallel data streams and modulate them to N orthogonal subcarriers. Thus spectrum utilization efficiency of the OFDM systems are high and high-speed data transmission is possible. However, with the OFDM systems using the same modulation method at all subcarriers, the error probability is dominated by the subcarriers which experience deep fades. Therefore, in order to enhance the performance of the system adaptive modulation is required, with which the modulation methods of the subcarriers are determined according to the estimated SNRs. The IEEE 802.11a system selects various transmission speed between 6 and 54 Mbps according to the modulation mode. There are three typical methods for SNR estimation: Direct estimation method uses the frequency domain symbols to estimate SNR directly by minimizing MSE (Mean Square Error), EVM method utilizes the distance between the demodulated constellation points and received complex values, and the method utilizing the Viterbi algorithm uses the cumulative minimum distance in decoding process to estimate the SNR indirectly. Through comparison analyses of three methods we propose a new SNR estimation method, which employs both the EVM method and the Viterbi algorithm. Finally, we perform extensive computer simulations to confirm the performance improvement of the proposed adaptive OFDM systems on the basis of IEEE 802.11a.

• Journal of the Society of Naval Architects of Korea
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• v.38 no.1
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• pp.99-107
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• 2001

Manufacture of fishing vessel is needed the effective material for light, strength, fire and corrosion of water in order to improve durability by high-speed and fishing. These fishing vessel can be divided into FRP and AI alloys fishing vessel. FRP fishing vessel is light and effective for strength but highly ignited and susceptible to heat during the manufacturing ship by-produce noxious component for human. In the case of a scrapped ship, it cause environmental pollution. On the other hand, aluminum is a material in return for FRP and has merit of high-strength and lightness. It's more heat proof and durable than FRP and superior to prevent from corrosion. Al alloys fishing vessel development is rising as an urgent matter. But, al alloy has some defect of bad weldability, welding transformation, cracks and overcost of construction. Therefore this study is to develop the new welding joint shape solving aluminum defects and mechanical behavior. First of all, strength was compared and reviewed by analysis of plate, stiffen plate, new model simplified by using plate theory. On the base of this result, plate and new model of temperature distribution, weld residual stress and strength of tensile, compressive force were compared and reviewed by finite element computer program has been developed to deal with heat conduction and thermal elasto plastic problem. Also, new model is proved application possibility and excellent mechanic by strength comparison is established to tensile testing result.

• Journal of Internet Computing and Services
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• v.14 no.4
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• pp.25-33
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• 2013

The procedure of the arbitration which is the tag collision is essential because the multiple tags response simultaneously in the same frequency to the request of the Reader. This procedure is known as Anti-collision and it is a key technology in the RFID system. In this paper, we propose the 4-Bit Pattern Slot Allocation(4-BPSA) algorithm for the high-speed identification of the multiple tags. The proposed algorithm is based on the tree algorithm using the time slot and identify the tag quickly and efficiently through accurate prediction using the a slot as a 4-bit pattern according to the slot allocation scheme. Through mathematical performance analysis, We proved that the 4-BPSA is an O(n) algorithm by analyzing the worst-case time complexity and the performance of the 4-BPSA is improved compared to existing algorithms. In addition, we verified that the 4-BPSA is performed the average 0.7 times the query per the Tag through MATLAB simulation experiments with performance evaluation of the algorithm and the 4-BPSA ensure stable performance regardless of the number of the tags.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.27-36
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• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• The KIPS Transactions:PartD
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• v.10D no.7
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• pp.1067-1076
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• 2003

Database sharing system (DSS) refers to a system for high performance transaction processing. In DSS, the processing nodes are locally coupled via a high speed network and share a common database at the disk level. Each node has a local memory and a separate copy of operating system. To reduce the number of disk accesses, the node caches database pages in its local memory buffer. In this paper, we propose a dynamic transaction routing algorithm to balance the load of each node in the DSS. The proposed algorithm is novel in the sense that it can support node-specific locality of reference by utilizing the primary copy authority assigned to each node; hence, it can achieve better cache hit ratios and thus fewer disk I/Os. Furthermore, the proposed algorithm avoids a specific node being overloaded by considering the current workload of each node. To evaluate the performance of the proposed algorithm, we develop a simulation model of the DSS, and then analyze the simulation results. The results show that the proposed algorithm outperforms the existing algorithms in the transaction processing rate. Especially the proposed algorithm shows better performance when the number of concurrently executed transactions is high and the data page access patterns of the transactions are not equally distributed.

• Journal of Internet Computing and Services
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• v.9 no.4
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• pp.11-20
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• 2008

IEEE 802.16e has adopted sleep mode to minimize energy consumption of mobile nodes with high speed mobility. If the Base Station (BS) has no data to be sent to a Mobile Subscriber Station (MSS) at the instant of ending sleep window of the MSS, the MSS increases its sleep window interval by double until the window interval reaches to the maximum sleep window interval. Thus, during the operation of sleep mode, MSS repeatedly performs switch on/off action until there exist frames to be received from BS. The switch on/off operation significantly consumes energy of MSS. To effectively deal with the energy of the MSS, this paper proposes an algorithm which decides the minimum sleep window interval that will be used in next sleep mode based on the current sleep window interval. We evaluate the performance of IEEE 802.16e sleep mode algorithm and our proposed algorithm in terms of energy consumption and blocking probability. Compared with the current sleep mode algorithm used in IEEE 802.16e, the proposed algorithm decreases the energy consumption by about 30% without increasing blocking probability.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.1
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• pp.279-285
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• 2017

The study on 'support for V2V(Vehicle to Vehicle) services based on LTE sidelink' has been carried out in 3GPP RAN working group. The conventional LTE sidelink technology is not adequate for high speed V2V communications because the conventional DM-RS(Demodulation Reference signal) structure is developed for pedestrian environment. While the typical speed of pedestrian environment is 3km/h, that of V2V communications is 120 km/h and the information on channel estimation is not sufficient with legacy DM-RS structure. In this paper, improved DM-RS structures for V2V communications that have rapid channel variation are introduced and the performance of channel estimation accuracy is analyzed. Simulation results show that the performance improvement of channel estimation can be achieved based on extended sub-carrier spacing structure resulted from reduced inter-carrier interference. However, the extended sub-carrier spacing requires the longer cyclic prefix and higher overhead. As a results of considerations on DM-RS modification, the sub-carrier spacing is maintained and the high density of DM-RS is applied for V2V communications.

• The Magazine of the IEIE
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• v.11 no.5
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• pp.42-50
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• 1984

국내의 다음세대 컴퓨터 개발을 위한 VLSI 설계와 CAD 분야에 대한 연구 방향을 제시한다. 연구의 목표는 국제적으로 경쟁할 수 있는 VLSI 설계능력과 백만개 정도의 트랜지스터로 자성된 회로를 경제적으로 설계하기 위한 CAD 기술과 System의 확립이다. ·새로운 회로 구조와 알고리즘에 대한 연구 · CAD 도구와 언어의 개발에 관한 첨단 CAD 기술개발연구 · VLSI 설계에 필요한 CAD 도구 이용과 개발에 필요한 표준 인터페이스, 네트워킹, 컴퓨팅 하드웨어. 시스템 소프트웨어에 대한 연구등의 부분으로 크게 나눌 수 있다. 이용 가능한 CAD system을 평가하고 개선하며 첨단 CAD에 대한 소프트웨어와 하드웨어에 대해 · 컴퓨팅 하드웨어 · 프로그램 분위기 · 네트워킹 능력 ·자료 교환을 위한 표준인터페이스 등에 관해 조사분석도 병행한다. CAD에 관한 세부적인 연구 과제는 · 시스템 사양언어 · 설계 검증 ·시스템시뮬레이션· 설계 합성 · 설계 해석· 설계 방법론·디바이스와 공정 모델링 프로그램 등이다. 고속 계산용 VLSI에 관한 구조와 알고리즘은 행렬 계산을 위한 ·분산 배열 처리 회로 ·시스토릭 (Systolic) 배열 회로 ·셀률라(Cellular) 논리 회로 · 3차원 배열 회로 와 · 비규칙적 계산 알고리즘을 갖는 VLSI가 있다. VLSI설계훈련과 CAD 기술 축적을 위해 CAD enter를 설립하여 전국적인 CAD 네트워킹을 관계 연구소와 여러 대학에 가설하며, MPC 계획을 추진한다. VLSI설계 가능성이 입증되면 VLSI 설계능력을 더욱 향상 시키기 위해 0.5∼1.0mm기술의 silicon faundary를 설립한다. 연구 개발 조직은 대학, 산업체. 연구소가 삼위일체가 되어 수행될 수 있도록 연구 개발 위원회를 설치 운영하며 경쟁적이며 경제적으로 연구 업무를 집행하는 것이 바람직하다.았다.형질에 관여하는 귀전자에 미치는 기구에 대하여 검토할 여타가 있다고 보여진다. 분해능의 특징으로 미루어 앞으로는 레이저를 이용한 계측 방법이 그 주류를 이룰 것으로 사료된다. 우선 본 해설은 기체의 온도 및 농도의 광학적 측정방법중 Raman산란광 검출법에 대하여 실제로 측정하는 입장에서 간단히 소개한다.lity)이, 높은 $GA_3$함량에 기인된다'는 주장은 본실험(本實驗)으로 부인(否認)되었다. 따라서, 응용학적(應用學的) 측면에서 고려해 볼 때, 리베스식물(植物)의 육종기간 단축을 위한 모든 화아분화(花芽分化) 촉진 조치는 P.J.-식물(植物)이 20. node이상 생육하였을 때 취하는 것이 효율적인 것으로 결론 지어진다.앞당겨진 7月 셋째 週였다. 8. Culex (Culex) tritaeniorhynchus summoro년의 最大發生 peak는 1981年, 1982年 모두 8月 둘째 週였다. 9. Anopheles (Anopheles) sinensis의 最大發生 peak는 1981年에 7月 다섯째 週, 1982年은 2週 앞당겨진 7月 셋째 週였다. 10. 重要 3種의 最大 peak를 比城하면 Culex (Culex) pipiens pallens와 Anopheles (Anopheles) sinensis는 1981年과 1982年 모두 最大 peak時期가 同一하였으며, Culex (Culex) tritaeniorhynchus summoro년는 2年間 모두 8月둘째 週에 나타났다.osterior to manubrium and anterior to aortic arch) replacing the normal mediastinal fat. (2) In benign thymoma, the marging of the mass was smooth and the normal fat

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.89-96
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• 2009

As increasing the number of digital control devices installed on aircrafts and their transmission speed, various digital data buses have been introduced to provide reliable and high-speed characteristics. These characteristics of avionics data bus are highly related on the fault-tolerant performance which can make minimize jitter and loss during data transfer. In this paper, we concerned about a new traffic shaping scheme for increasing the reliability of Avionics Full Duplex Switched Ethernet (AFDX) systems based on ARINC 664 standard. We note that the conventional AFDX with a single regulator per virtual link system may produce aggregated traffics as the number of virtual links increasing. The aggregated traffic results in large jitters among frames. To remedy for the jitter and loss of data, we propose a dual regulator scheme for the AFDX system. The purpose of the additional regulator is to additionally regulate aggregated traffics from a number of per virtual link regulators. Using NS-2 simulator, we show that the proposed scheme provides a better performance than the single regulator one. It is worthwhile note that the proposed AFDX with Dual Regulator scheme can be employed to not only aircraft networks but other QoS sensitive networks for robot and industrial control systems.