• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.71-78
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• 2009

An 8${\times}$8-Gb/s/channel 4-PAM transceiver was designed for high speed memory applications by using 70nm DRAM process with 1.35V supply. An asymmetric 4-PAM signaling scheme is proposed to increase the voltage and time margin of upper and lower eyes in 3-class eye opening. A mathematical basis shows that this scheme statistically reduces 33% of reference noise effect in a receiver. Also, an adaptive pre-emphasis scheme, which utilizes a lone-bit pulse with integrator at the receiver, is introduced to reduce ISI for a simple DRAM channel. In this scheme, an integrating clock timing calibration by using a pre-determined pattern is proposed for the optimum ISI measurement.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.440-447
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• 2002

This paper considerated about exact flow volume calculation method from factors having an influence on measurement and introduced in anesthesia ventilator realized spirometry system. System used differential pressure sensing method with factors, that is temperature, pressure, gas density, humidity and mucus etc. System optimized for low power system for mobile system. System composed analog interface part, signal processing part, display part. Analog interface part have differential pressure flow sensor and defferential pressure sensor. Signal processing part have AVR processor for low power system display part use serial port (RS232, SPT). so it display at pc monitor or send to anesthesia ventilator. System is stable by linearizing 2th characteristics of flow-differential pressure, auto correction of sensor. Noise reduced by algorithm with analog filter and digital processing. Small, light, low power system is good at mobile system and applied to patient in emergency or mobile. and, System is useful at anesthesia ventilator by using flow sensor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.879-886
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• 2008

This paper addresses the analysis and the design optimization of differential interconnects for Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential flexible printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, time-domain transient simulations, and S-parameter simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. The 10% change in trace width produced change of approximately 6% and 5.6% in differential impedance for trace thickness of $17.5{\mu}m$ and $35{\mu}m$, respectively. The change in the trace space showed a little change. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.11
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• pp.28-36
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• 1998

In the CDMA mobile communication system with asynchronous mode among base stations, the initial PN code acquisition method using a matched filter can be considered for the rapid PN code synchronization acquisition in the handoff region. In the model of the noncoherent QPSK/DS-SS under the Rayleigh fading channel, the mean acquisttion time of the matched filter is analyzed to have a shortened time in proportion to the length of matched filter to be compared with the serial correlation method. In this paper to improve the HW complexity of the conventional matched device which enables the repeated correlation process, is designed and its function is verified through the FPGAsimulation using Altera MaxPlus Ⅱ.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.2 s.332
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• pp.49-59
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• 2005

An adaptive hybrid beamformer is proposed to improve the reception performance of the advanced television system committee (ATSC) digital television (DTV) in a mobile environment. Dynamic multipaths and Doppler shifts severely degrade the reception performance of the ATSC DTV receiver. Accordingly, a hybrid beamformer, called a Capon and least mean square (CLMS) beamformer, is presented that uses direction of arrival (DOA) information and the least mean square (LMS) beamforming algorithm. The proposed CLMS algerian efficiently removes dynamic multipaths and compensates for the phase distortion caused by Doppler shifts in mobile receivers. After the CLMS beamformer is operated, the subsequent use of an equalizer removes any residual multipath effects, thereby significantly improving the performance of DTV receivers. The performances of the proposed CLMS, Capon, and LMS beamformersare compared based on computer simulations. In addition, the overall performance of the CLMS beamformer followed by an equalizer is also considered.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.4
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• pp.41-49
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• 2004

In this paper, a design and measurement method for FPGA embedded gigabit-transceiver is presented. Altera's Stratix GX device which is general purpose transceiver called GXB was used for implementing PCI Express transceiver. PCI Express is the generation high performance serial I/O bus used to interconnect peripheral devices. After GXB was set follow by PCI Express specifications, the design has been verified by timing simulation and implemented as hardware. We tested it as follow. First GXB internal digital and analog block test second GXB transmitter signal integrity test called Eye mask test, third GXB high-speed serial I/O buffer and on-chip termination test and the last GXB protocol test. This paper shows all the design and measurement procedure about FPGA embedded gigabit-transceiver.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.184-193
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• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.