• The Journal of the Korea Contents Association
• /
• v.8 no.5
• /
• pp.72-81
• /
• 2008

High Performance DSP usually supports cache and internal memory. For an optimal implementation of a multimedia stream application on such a high performance DSP, one needs to utilize the cache and internal memory efficiently. In this paper, we investigate performance analysis of cache, and internal memory configuration and placement necessary to achieve an optimal implementation of multimedia stream applications like motion picture encoder on high performance DSP, TMS320C6000 series, and propose strategies to improve performance for cache and internal memory placement. From the results of analysis and experiments, it is verified that 2-way L2 cache configuration with the remaining memory configured as internal memory shows relatively good performance. Also, it is shown that L1P cache hit rate is enhanced when frequently called routines and routines having caller-callee relationships with them are continuously placed in the internal memory and that L1D cache hit rate is enhanced by the simple change of the data size. The results in the paper are expected to contribute to the optimal implementation of multimedia stream applications on high performance DSPs.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
• /
• 2003.05a
• /
• pp.8-11
• /
• 2003

본 연구는 AC서보 모터의 벡터 제어를 구현하는데 있어 디지털 제어에 의한 시간 지연 및 Af) 변환기, QEP(Quadrature Encoder Pulse Circuit)등 주변 소자의 시간 지연에 의한 노이즈를 최소화하지 위하여 고성능 저 전압형 DSP인 TMX320F2812를 사용하였다. TMX320F2812는 150MIPS의 빠른 연산 속도와 12비트의 AD 컨버터, QEP회로는 물론 공간 전압 벡터 PWM을 발생시킬 수 있는 기능을 가진 모터 제어용 원친 DSP이다. 이와 같이 주변 회로들을 내장한 고성능 DSP의 사용은 모터 제어부의 하드웨어적인 구성을 간소화 시키고 이로 인한 비용 절감을 얻을 수 있다. 또한 전류 샘플을 위한 필터 부분을 디지털 필터화 하여 전류 샘플링 노이즈를 제거하였고, 옵셋 전압을 이용한 SVPWM을 구현하여 연산 시간을 대폭 단축 하였다. TMX320F2812의 단점인 고정 소수점 연산에 대해서는 각 변수에 대한 스케일링을 통해 유효 자리를 확보하였다.

• Journal of KIISE:Software and Applications
• /
• v.34 no.5
• /
• pp.487-501
• /
• 2007

To achieve high resource utilization for multi-issue DSPs, production compiler commonly includes variants of iterative modulo scheduling algorithm. However, excessive cyclic data dependences, which exist in communication and media processing loops, unduly restrict modulo scheduling freedom. As a result, replicated functional units in multi-issue DSPs are often under-utilized. To address this resource under-utilization problem, our paper describes a novel compiler preprocessing strategy for effective modulo scheduling. The preprocessing strategy proposed capitalizes on two new transformations, which are referred to as cloning and dismantling. Our preprocessing strategy has been validated by an implementation for StarCore SC140 DSP compiler.

• Proceedings of the KIEE Conference
• /
• 2002.11d
• /
• pp.76-79
• /
• 2002

본 논문에서는 고성능 AC 서보 모터에 대하여 제어 시스템을 구현하고, 제어기를 설계한다. 하드 웨어구성은 모터 전용 저전압 DSP칩인 TMS320LF2407 칩을 이용한다. TMS320LF2407는 최근의 저전력 구동 추세에 따라 3.3V를 구동 전압으로 이용하는 DSP 칩이다 연산 처리 속도는 40MIPS로 빠른 연산 처리능력을 가지고 있지만 주변 소자들과의 인터페이스(보통 5V로 동작)와 노이즈에 대한 대책을 고려하여야 한다. 본 논문에서는 이러한 전압 호환과 노이즈를 가능한 제거한 서보 모터 제어기를 구성하며, 또한 유효 전압 인가시간의 관점에서 바라본 개선된 공간 벡터 PWM방식을 적용함으로써 계산과정과 프로그램을 간단히 하고, 전류제어를 소프트웨어 방식으로 처리하여 복잡한 하드웨어를 간략화 시키고자 한다 이런 과정에 의하여 앞으로 요구될 수 있는 고성능 다기능을 위한 효용성을 높이고자 한다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.8
• /
• pp.1450-1455
• /
• 2007

Recently DSP chips are widely used in high quality car audio to achieve high quality sound and to process various sound sources, e.g. navigation, cell phones. In this paper, we developed a set of design tools useful for developing high quality car audio systems using Philips' SAF7730 car audio chips. The tool is consist of the GUI(Graphic User Interface) program running on the Windows operating system and the interface board which performs data conversion between RS232C and I2C protocols. The developed system has been successfully applied to commecial car audio design.

• Journal of the Korea Computer Industry Society
• /
• v.9 no.3
• /
• pp.129-136
• /
• 2008

This paper implement image gradient detection algorithm with high-performance DSP. First the NTSC color image convert to B/W image. The image gradient detect with Hough transform after edge detection image from the B/W images. The value of image gradient detection control the servo motor to original position of the NTSC camera if camera base to the left or right tilt.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.4C
• /
• pp.388-397
• /
• 2002

We designed a SIMD-DSP/FPU that can efficiently improve multimedia processing performance when integrated into high-performance embedded microprocessors. We proposed partitioned architectures and new schemes for several functional units to reduce chip area. Sharing functional units reduces the area of FPU significantly. The proposed architecture is modeled in HDL and synthesized with a 0.35$\mu\textrm{m}$ standard cell library. The chip area is estimated to be about 100,000 equivalent gates. The designed unit can run at higher than 50MHz clock frequency of CPU core under the worst-case operating conditions.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.67-70
• /
• 2000

DSP is used for processing the digital data in such as the multimedia applications. Because the digital data of high rate is demanded more and more, high performance is increasingly required in DSP. In this paper, we discuss important issues for development of high performance DSP, analyze architectures of several commercial DSP chips, and propose a new architecture. Finally, we show that the new architecture has the highest performance.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.2
• /
• pp.72-81
• /
• 2002

A new high-performance DSP architecture is proposed, which behaves as a coprocessor of a 32bit microcontroller. Because the proposed DSP architecture is a dual MAC(Multiply and Accumulate) DSP architecture, it can process efficiently a number of SOP(sum of product) operations used in many DSP applications. In order to efficiently perform other operations such as pure additions without any restriction, a MAC is composed of a multiplier and a ALU placed in parallel. In addition, it is a 3-way superscalar architecture, which can issue 3 instructions at a time. The benchmark results with 3 thor dual MAC DSPs show that the proposed DSP has the best performance. Futhermore, it is proven that the proposed DSP is more efficient in memory usage, although the performance is comparable in some algorithms such as Viterbi decoding and FFT butterfly.

• Proceedings of the KIEE Conference
• /
• 2003.04a
• /
• pp.258-261
• /
• 2003

This paper is a studying of the vector control of AC servo motor using a high performance DSP(TMX320F2812). This DSP has many special peripheral circuits to drive a AC Servo motor as AD converter, QEP and so on. It makes us reduce the time of developing a control system and also can be simple size controller. We use vector control algorithm for instantaneous torque control and SVPWM algorithm by offset voltage methods.