• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.50-57
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• 2009

This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.425-434
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• 2007

Even though Internet backbone speeds have increased in the last few years due to projects like Internet 2 and NGI, many high performance distributed applications are able to achieve only a small fraction of the available bandwidth. The cause of such problem is due to a character of TCP/IP. The primary goal of this protocol is reliable data transmission. Therefore high speed data transmission didn't be considered when TCP/IP is designed. Hence several researchers have been studied in order to solve the problem of TCP/IP. One of these research results, parallel transfer technique, solves this problem to use parallel TCP connections on application level. Additionally, this technique is compatibility. Recently, these researchers have been studied a mechanism to decide the number of parallel TCP connections. However, some researchers reported the number of parallel TCP connection base on only empirical results. Although hardware performance of host affects transmission rate, the hardware performance didn't be considered in their works. Hence, we collect all data related to transmission rate, such as hardware state information (cpu utilization, interrupt, context switch). Then, we analyzed collected data. And, we suggest a new mechanism determining number of parallel TCP connections for maximization of performance based on our analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.24-31
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• 2007

Up to date, a lot of bus protocol and bus architecture are released though most of them are based on the shared bus architecture and inherit the limitation of performance. SNP (SoC Network Protocol), and hence, SNA (SoC Network Architecture) which are high performance on-chip-bus protocol and architecture, respectively, have been proposed to solve the problems of the conventional shared bus. We refine the SNA specification and improve the performance and functionality. The performance of the SNA is improved by supporting simultaneous routing for bus request of multiple masters. The internal routing logic is also improved so that the gate count is decreased. The proposed SNA employs XSNP (extended SNP) that supports almost perfect compatibility with AMBA AHB protocol without performance degradation. The hardware complexity of the improved SNA is not increased much by optimizing the current routing logic. The improved SNA works for IPs with the original SNP at its best performance. In addition, it can also replace the AMBA AHB or interconnect matrix of a system, and it guarantees simultaneous multiple channels. That is, the existing AMBA system can show much improved performance by replacing the AHB or the interconnect matrix with the SNA. Thanks to the small number of interconnection wires, the SNA can be used for the off-chip bus system, too. We verify the performance and function of the proposed SNA and XSNP simulation and emulation.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.3
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• pp.166-177
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• 2006

The cache size tends to grow in the embedded processor as technology scales to smaller transistors and lower supply voltages. However, larger cache size demands more energy. Accordingly, the ratio of the cache energy consumption to the total processor energy is growing. Many cache energy schemes have been proposed for reducing the cache energy consumption. However, these previous schemes are concerned with one side for reducing the cache energy consumption, dynamic cache energy only, or static cache energy only. In this paper, we propose a hybrid scheme for reducing dynamic and static cache energy, simultaneously. for this hybrid scheme, we adopt two existing techniques to reduce static cache energy consumption, drowsy cache technique, and to reduce dynamic cache energy consumption, way-prediction technique. Additionally, we propose a early wake-up technique based on program counter to reduce penalty caused by applying drowsy cache technique. We focus on level 1 data cache. The hybrid scheme can reduce static and dynamic cache energy consumption simultaneously, furthermore our early wake-up scheme can reduce extra program execution cycles caused by applying the hybrid scheme.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.293-299
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• 2007

Intelligent pipeline inspection gauges (PIGs) are inspection vehicles that move along within a (gas or oil) pipeline and acquire signals (also called sensor data) from their surrounding rings of sensors. By analyzing the signals captured in intelligent PIGs, we can detect pipeline defects, such as holes and curvatures and other potential causes of gas explosions. There are two major data access patterns apparent when an analyzer accesses the pipeline signal data. The first is a sequential pattern where an analyst reads the sensor data one time only in a sequential fashion. The second is the repetitive pattern where an analyzer repeatedly reads the signal data within a fixed range; this is the dominant pattern in analyzing the signal data. The existing PIG software reads signal data directly from the server at every user#s request, requiring network transfer and disk access cost. It works well only for the sequential pattern, but not for the more dominant repetitive pattern. This problem becomes very serious in a client/server environment where several analysts analyze the signal data concurrently. To tackle this problem, we devise a fast in-memory cache manager, called T-Cache, by considering pipeline sensor data as multiple time-series data and by efficiently caching the time-series data at T-Cache. To the best of the authors# knowledge, this is the first research on caching pipeline signals on the client-side. We propose a new concept of the signal cache line as a caching unit, which is a set of time-series signal data for a fixed distance. We also provide the various data structures including smart cursors and algorithms used in T-Cache. Experimental results show that T-Cache performs much better for the repetitive pattern in terms of disk I/Os and the elapsed time. Even with the sequential pattern, T-Cache shows almost the same performance as a system that does not use any caching, indicating the caching overhead in T-Cache is negligible.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.4
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• pp.2217-2224
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• 2014

This paper deals with system development which measures 12 channel ECG using medical analog front end(AFE) and discriminates arrythmia through signal analysis. Recently, occurrences of cardiac arrest have been increased. So the need of system that diagnoses an arrythmia which results in cardiac arrest is increasing. There are some drawbacks of conventional 12 channel ECG system that it occupies bulk and consists of complicated circuit. To improve those, we made up the system composed of medical AFE, algorithm for discriminating arrythmia and DSP for signal processing. This system can be monitored 12 channel ECG waveforms and the discriminant analysis result of arrhythmia through 7" LCD and received the input through touch pannel. In this study, we conducted normal operation test about output signal of ECG simulator(normal/abnormal ECG signal) to verify the implemented system and performance evaluation of the optimization process for applying arrhythmia algorithm to an embedded environment.

• Journal of the Korean Recycled Construction Resources Institute
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• v.2 no.3
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• pp.173-179
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• 2014

This is an experimental study for recycling coal ash left over from coal use as a potential fine aggregate in concrete. Coal ash is generally divided into either fly ash or bottom ash. Fly ash has been utilized as a substitution material for cement in concrete mixes. On the other hand, bottom ash has the problem of low recycling rates, and thus it has been primarily reclaimed. This study partially substituted fine concrete aggregates with bottom ash to increase its application rate and therefore its recycling rate; its suitability for this purpose was confirmed. The concrete's workability dropped noticeably with increasing bottom ash content when a fixed water-cement ratio of concrete mix was used. Thus, concrete mixes with higher ratio levels are required. To address this problem, concrete was mixed using a polycarboxylate high-range water reducing agent. The fluidity and air entrainment immediately after mixing the concrete and 1 h after mixing were measured, thereby replicating the time concrete is placed in the field when produced either in a ready-mixed concrete or in a batch plant. As a result of this research, the workability and air entrainment were maintained 1 h after mixing for a concrete mixture with approximately 30% of its fine concrete aggregates substituted with the bottom ash. A slight drop in compression strength was seen; however, this confirmed that potential of using bottom ash as a fine aggregate in concrete.

• Journal of Navigation and Port Research
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• v.27 no.4
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• pp.443-447
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• 2003

In this work. using 0.2 GaAs modulation doped FET(MODFET), a high performance DBS downconverter MMIC was developed for direct broadcasting satellite (DBS) application. Without LNA, the downconverter MMIC showed a very low noise of 4.8 dB, which is lower by 3 dB than conventional ones. A low LO power of -10 dBm was required for the normal DBS operation of the downconverter MMIC. which reduced the power consumption via a removal of LO amplifier on MMIC. It required only a low power consumption of 175 mW, which is lower than 70 percent of conventional ones. The LO leakage power at IF output was suppressed to a lower level than 30 dBm, which removes a bulky LO rejection filter on a board. The fabricated chip, which include a mixer, If amplifiers. LO rejection filter, and active balun, exhibited a small size of $0.84{\times}0.9\textrm{mm}^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.11
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• pp.902-915
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• 2017

In recent years, mobile devices have become increasingly multi-functional and high performance, resulting in a dramatical increase in processing speed. On the other hand, the size of device is reduced, circuits inside the device are more easily exposed to electromagnetic interference radiated from antenna or adjacent circuits, degrading the system performance. To prevent this, it is necessary to design the device considering the electromagnetic characteristics with EM simulation at the design stage of product. However, the EM simulation takes a long analysis time and require high-level system resources for fast analysis. In this paper, an equivalent circuit modeling method for a round wire is proposed using a PEEC method and the electromagnetic coupling from a dipole antenna to a transmission line is analyzed in frequency domain. And compared with the result of electromagnetic simulator. As a result, PEEC method shows good agreement with those of electromagnetic simulation, in a much more short time.