• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.110-116
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• 2014

Pattern matching algorithms are widely used in computer security systems such as computer networks, ubiquitous networks, sensor networks, and so on. However, the advances in information technology causes grow on the amount of data and increase on the computation complexity of pattern matching processes. Therefore, there is a strong demand for a novel high performance pattern matching algorithms. In light of this fact, this paper newly proposes a suffix tree based pattern matching algorithm. The suffix tree is constructed based on the suffix values of all patterns. Then, the shift nodes which informs how many characters can be skipped without matching operations are added to the suffix tree in order to boost matching performance. The proposed algorithm reduces memory usage on the suffix tree and the amount of matching operations by the shift nodes. From the performance evaluation, our algorithm achieved 24% performance gain compared with the traditional algorithm named as Wu-Manber.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.37 no.4
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• pp.1-8
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• 2000

The massive growth of the internet and the world-wide-web leads us to research the programming languages for the development of applications in heterogeneous, network-wide distributed environments. Java is an object-oriented language for such a environment and the Java programming language environment provides a portable, interpreted, high-performance, simple programming language. Bytecode is an intermediate code for Java language and it enables the development of applications on multiple platform in heterogeneous, distributed networks. But it takes much time to execute Bytecode because of using an interpretation method. In this paper, we design and implement a retargetable code generation system which can be systematically reconfigured to generate code for a variety of distinct target computers. From the system, we realize the code generation system which translates the Bytecode being produced by Java compiler into Pentium target code. We use ACK code generation system to do the work easily.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.57-65
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• 2002

In this paper, a 2.5V 10-bit 300MSPS CMOS D/A Converter is described. The architecture of the D/A Converter is based on a current steering 8+2 segmented type, which reduces non-linearity error and other secondary effects. In order to achieve a high performance D/A Converter, a novel current cell with a low spurious deglitchnig circuit and a novel inverse thermomeer decoder are proposed. To verify the performance, it is integrated with $0.25{\mu}m$ CMOS 1-poly 5-metal technology. The effective chip area is $1.56mm^2$ and power consumption is about 84mW at 2.5V power supply. The simulation and experimental results show that the glitch energy is 0.9pVsec at fs=100MHz, 15pVsec at fs=300MHz in worst case, respectively. Further, both of INL and DNL are within ${\pm}$1.5LSB, and the SFDR is about 45dB when sampling, frequency, is 300MHz and output frequency is 1MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.66-73
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• 2002

As floating-point operations become widely used in various applications such as computer graphics and high-definition DSP, the needs for fast division become increased. However, conventional floating-point dividers occupy a large hardware area, and bring bottle-becks to the entire floating-point operations. In this paper, a high-performance and small-area floating-point divider, which is suitable for embedded processors, is designed using he series expansion algorithm. The algorithm is selected to utilize two MAC(Multiply-ACcumulate) units for quadratic convergence to the correct quotient. The two MAC units for SIMD-DSP features are shared and the additional area for the division only is very small. The proposed divider supports all rounding modes defined by IEEE 754 standard, and error estimations are performed for appropriate precision.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.1
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• pp.51-56
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• 1981

A new I2L process for a high performance I2L structure is proposed. The modifiedstructure consists of a heavily doped extrinsic base and lowly doped intrinsic base where the collector regions are self-alignment with the intrinsic base regions. The proposed process untilizes spin-on sources as the diffusion sources and the self-alignment of collectors is achieved by using the hardened spin-on source as a diffusion mask. Test devices including a 13-stage ring oscillator have been fabricated by the proposed process on n/n+ silicon wafers with 6.5$\mu$m epitaxial layer. The maximum upward current gain of npn transistors is 8 for a three collector I2L cell. The speed-power product and minimum propagation delay for a one collector structure are 3.5 pJ and 50 ns, respectively.

• Journal of Broadcast Engineering
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• v.16 no.5
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• pp.801-810
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• 2011

This paper proposes a new lossless data embedding algorithm on spatial domain of digital images. A single key parameter is required to embed and extract data in the algorithm instead of embedding any additional information such as the location map. A $3{\times}3$ window slides over the cover image by one pixel unit, and one bit can be embedded at each position of the window. So, the ideal embedding capacity equals to the number of pixels in an image. For further increase of embedding capacity, new weight parameters for the estimation of embedding target pixels have been used. As a result, significant increase in embedding capacity and better quality of the message-embedded image in high capacity embedding have been achieved. This algorithm is verified with simulations.

• Journal of the Korean Chemical Society
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• v.30 no.2
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• pp.216-223
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• 1986

Separation of optical isomers of DNS derivatized amino acids by a reversed-phase high-performance liquid chromatography has been studied by adding a complex of an optically active amino acid (L-arginine) with the metal ion (Cu(II), Zn(II), Cd(II), Ni(II)) to the mobile phase. The separations are affected by the concentrations of acetonitrile, chelate and buffer. They are also affected by the pH and the kinds of metal and buffer. A separation mechanism, which is based on steric effect of the ligand exchange reaction for the formation of ternary complexes by the D,L-DNS-amino acids and the chiral additive associated with the stationary phase, is proposed to interpret the elution behaviors of D, L-dansyl-amino acids.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.21-28
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• 1999

A new method of making high speed self-aligned ESD (Elevated Source/Drain) MOSFET is proposed. Different from the conventional LDD (Lightly-Doped Drain) structure, the proposed ESD structure needs only one ion implantation step for the source/drain junctions, and makes it possible to modify the depth of the recessed channel by use of dry etching process. This structure alleviates hot-carrier stress by use of removable nitride sidewall spacers. Furthermore, the inverted sidewall spacers are used as a self-aligning mask to solve the self-align problem. Simulation results show that the impact ionization rate ($I_{SUB}/I_{D}$) is reduced and DIBL (Drain Induced Barrier Lowering) characteristics are improved by proper design of the structure parameters such as channel depth and sidewall spacer width. In addition, the use of removable nitride sidewall spacers also enhances hot-carrier characteristics by reducing the peak lateral electric field in the channel.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.4
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• pp.17-22
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• 2009

FlexRay is a new standard of network communication system which provides solutions to the degradation problems generated by many ECU (Electronic Control Unit) connections in automobiles and automation systems. The upper bound of the data rate is 10Mbps and it provides two channels for redundancy In this paper, FlexRay system is first designed using SDL. For hardware implementation, FlexRay system is designed using Verilog HDL based on the SDL design result. The designed system is synthesized using Synopsys Design Compiler with the Magna/Hynix 0.18 um cell library. In this paper, to construct a FlexRay network, active star is used since active star systems can provide high speed data transmission up to 10Mbps. The performance of the star network is tested using one transmitter node and two receiver nodes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.1-6
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• 2010

H.264 video coding standard is widely used due to the high compression rate and quality. H.264 decoders usually have pipeline architecture by a macroblock or a $4{\times}4$ sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and the requirement of high data bandwidth and high performance processing units. We propose adaptive pipeline architecture for H.264 decoders for efficient decoding and lower the requirement of the bandwidth for the memory bus. Parameters and coefficients are delivered using hand-shaking communication through dedicated interconnections and frame pixel data are transferred using AMBA AHB network. The processing time of each block is variable depending on the characteristics of images, and the processing units start to work whenever they are ready. An H.264 decoder is designed and implemented using the proposed architecture to verify the operation using an FPGA.