• KASI NEWSLETTER
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• s.48
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• pp.1-8
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• 2005

신년사/ 천문연 영문 명칭 변경/ 한국우주전파관측망(KVN) 기공식/ "04년도 실적평가 및 "05년도 선정평가 공개발표회/ 박상대 이사장 UST, 특별강좌/ 박상대 이사장, 기초연 차세대 연구기반동 기공식 축사/ 조직개편/ 2005 역서, 천문력 발행/ 2004년 동계 교원 천문 연수 실시/ 한-일 VLBI 연구협력을 위한 공동 모임/ 과학기술인공제회 회원 가입신청/ 직원동정/ 학회동정/ 콜로키움/ 일본의 적외선 우주망원경 ASTRO-F/ 2004 천문학.우주과학 및 관련기술에 대한 한일 공동강의/ 레몬산천문대 원격관측 시연회 및 현판식/ 새로 발견된 5개의 소행성에 한국의 과학기술자 이름 헌정/ FIMS이용, 세계최초 돛자리초신성 전체 영상관측/ 크리미아천문대와 공동연구 협정 체결/ 천문 계산용 고성능 PC 클러스터 구축/ 중앙전파관리소와 우주전파기술 교류에 관한 협약 체결/ 세종대학교와 망원경 운영 협정서 체결/ 일본 우주과학연구본부와 상호협약서 체결/ 연구원 창립 30주년 기념식 거행

• The Transactions of the Korea Information Processing Society
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• v.5 no.7
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• pp.1791-1800
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• 1998

본 논문에서는 Mamdani 방법과 Koczy 방법의 퍼지 추론 알고리즘에 대햇 병렬머신에 적합한 병렬 퍼지 추론 방법을 제안하고, 효율적인 병렬 퍼지 아키텍처를 설계한다. 제안된 아키텍처는 비교적 높은 성능을 갖고, 확장이 용이한 구조로서, 여러개의 FPE(Fuzzy Processing Element), CP(Control Processor), 메모리 모듈, 상호연결망 및 Min 회로로 구성되어 있다. 이러한 구조의 특징은 iqjsWo의 FPE는 I번째의 전건부 및 I번째의 후건부의 처리만을 수행하기 때문에 전건부, 변수들의 처리는 각각 병렬도 수행되고, 후건부의 처리도 또한 각각 병렬로 수행된다. 따라서 프로세서의 활용도가 높아지며, 전건부와 후건부의 변수, 퍼지규칙의수에 관계없이 쉽게 구성할 수 있다. 이러한 구조는 실시간에 고속추론을 요하는 시스템 또는 전건부와 후건부의 변수가 많은 대규모 전문가 시스템에 사용되어 질 수 있으며, MISO(Multiple-input, Single-output) 시스템보다 MIMO(Multiple-input, Multiple-output) 시스템에 특히 적합하다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.1
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• pp.69-72
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• 2004

A bandpass filter has been designed by employing the PBG structure and the aperture on the ground together in this paper. The harmonics of band pass filter have been suppressed by employing the PBG structure and the bandwidth of it has been broadened by using the aperture on the ground. The three kinds of PBG structures has been combined to suppress the harmonics of the filter The center frequency of filter is 2.2 GHz and the bandwidth has been increased from $40\%$ by the aperture and all harmonics were suppressed about 35dBc by the PBG. The insertion loss has been reduced 3.0dB to 2.6dB.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.4
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• pp.242-250
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• 2007

Wireless sensor networks are subject to highly heterogeneous system requirements in terms of their functionality and performance due to their broad application areas. Though the heterogeneity hinders the opportunity of developing a single universal platform for sensor networks, efforts to provide uniform, inter-operable and scalable ones for sensor networks are still essential for the growth of the industry as well as their technological advance. As a part of our work to develop such a robust platform, this paper presents the software architecture for sensor nodes with focus on our sensor node operating system and its configuration methodology. Addressing principle issues in its design space which includes programming, execution, task scheduling and software layer models, our architecture is highly reconfigurable with respect to system resources and functional requirements and also highly efficient in supporting multi-threading under small system resources.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.3
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• pp.131-143
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• 1998

This paper presents a high performance disparity extraction algorithm that generate a dense and accurate disparity map using low-resolution disparity histogram. Disparity distribution of background and object areas can besegmented from low-resolution disparity histogram. These information can be used to reduce the search area and search range of the high-resolution image resulting reliable disparity information in high speed. The computationally efficient matching pixel count(MPC) similarity measure technique is useed extensively toremove the redundancies inherent in the area-based matching method, and also results robust matching at the boundary region. Resulting maches are further improved using iterative support algorithm and post processing. We have obtained good results on randomdot stereogram and real images obtained in our carmera system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.25-30
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• 2009

We have developed recycling technology of ethylen carbonate to use in photoresist stripping and cleaning process, which will be core processing technology for high performance and low price semiconductor and LCD fabrication. Using this technology, it is possible for semiconductor wafer and LCD planer to process more rapid and chip, and productivity will be improved.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.117-123
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• 2016

In general, PCM (Phase Change Memory) is unsuitable as a main memory because it has limitations: high read/write latency and low endurance. However, the DRAM&PCM hybrid memory with the same level is one of the effective structures for a next generation main memory because it can utilize an advantage of both DRAM and PCM. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an access time and write count of PCM by using an effective page replacement. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM access count by around 60% and the PCM write count by 42% given the same PCM size, compared with Clock-DWF algorithm.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.19-21
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• 1997

This paper treated a new method that generates the dipole magnetic field for high speed machines by using Halbach array, which was suggested by Klaus Halbach. The Halbach array can produce the various field distribution without magnetic materials. Therefore, the iron losses can be reduced. This paper presented the magnetic characteristics on both linear and cylindrical Halbach array. And the Halbach array for dipole field was manufactured with Nd-Fe-B magnets having 1.17(T), the measured flux density was compared the theoretical values acquired by three dimensional FEM analysis. Finally, the magnetic characteristics of Halbach array were compared with those of other conventional dipole field systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.394-397
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• 2003

Since the speed of operation in the system has been increasing rapidly, chips should have been synchronized. Then, synchronized circuits such as PLL (Phase Locked Loop), DLL (Delay Locked Loop) are used. VCO (Voltage Controled Oscillator) generated a frequency in the PLL has disadvantage such as jitter accumulation. On the other hands, VCDL (Voltage Controled Delay Line) used at DLL has an advantage which has no jitter accumulation. In this paper, a new and improved VCDL structure is suggested.

• Proceedings of the KSME Conference
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• 2000.11a
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• pp.829-836
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• 2000

High performance laser printer requires high speed scanning motor, which can operate up to 40,000 rpm. However, development of high speed scanning motor has been restricted due to the practical problems such as use of high speed bearing, compact circuit design and high cost. In this study, we designed a high speed scanner motor for use on laser scanning unit and discussed some design principles including the reduction method of cogging torque of the motor, development of hemispherical aerodynamic bearing, windage loss estimation, and operating circuit design to reduce noise.