• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.124-130
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• 2013

In this paper, a new motion estimation algorithm with low-computational complexity is proposed to improve the performance of H.264/AVC. The proposed architecture uses the directions of the median motion vector which is computed by the motion vectors of the three neighbor macroblocks in Integer Motion Estimation. By using the directions of the vector, the proposed architecture has a single computational level instead of multi-computational levels in Integer Motion Estimation. The proposed motion estimation is synthesized using the TSMC 0.18um standard cell library. The synthesis result shows that the gate count is about 217.92K at 166MHz and it was improved about 69% compared with previous one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.56-70
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• 2010

Rendering technique generating 2 dimensional image to give reality and high performance graphical processor for efficient processing of massive data are necessary to support realistic 3 dimensional graphical image. Recently, graphical hardwares have evolved rapidly. This enables high quality rendering effect that we were unable to process in realtime. Improving shading technique enabled us to render realistic images but still much time is required for this process. Multiple operational units are being integrated in a graphical processor for effective floating point operation using massive data to process almost real looking images. In this paper, we have designed and implemented a special functional unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed special functional unit. Hardware resource usage rate and execution speed are measured implementing directly on FPGA Virtex-4(xc4vlx200).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.21-29
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• 2012

This paper presents optimized searching technique to improve the performance of H.264/AVC. By using the proposed forward and backward searching algorithm, redundant cycles of latency for data reordering can be removed. Furthermore, in order to reduce the total number of execution cycles of CAVLC encoder, early termination mode and two stage pipelined architecture are proposed. The experimental result shows that the proposed architecture needs only 36.0 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 57.8% than that of previous designs. The proposed CAVLC encoder was implemented using Verilog HDL and synthesized with Magnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 17K with 125Mhz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.31-40
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• 2005

The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of mobile computing applications. In this paper, we (i) motivate the post-mask-tooling performance enhancement technique combined with the MTCMOS leakage current suppression technology, and (ii) develop a practical MTCMOS ASIC design methodology which fine-tunes and integrates best-in-class techniques and commercially available tools to fix the new design issues related to the MTCMOS technology. Towards validating the proposed techniques, a Personal Digital Assistant (PDA) processor has been implemented using the methodology, and a 0.18um Process. The fabricated PDA processor operates at 333MHz which has been improved about $23\%$ at no additional cost of redesign and masks, and consumes about 2uW of standby mode leakage power which could have been three orders of magnitude larger if the MTCMOS technology was not applied.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.135-140
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• 2015

Web-services employ XML that is the well-formed structure as a de-facto standard to represent data. SOAP or REST is one of the representative web-services using XML based massage passing systems. The XML parser can be divided into event driven and DOM tree. A streaming parser as an event driven is widely used for high-speed parsing. Since the streaming parser processes XML documents in sequence, they have any limitation to improve system performance. In order to improve speed of streaming XML parser, we present multibyte based streaming XML hardware parser using the element analyzer instead of the state machine. Compared to other parsers, the proposed MStreXHP can achieve about 2.72 times improvement in the number of clock cycles to be consumed in comparison of characters and sustain about 7.8Gbps throughput. Therefore, our MStreXHP is desirable for the streaming XML hardware parser on high-performance systems.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.3
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• pp.59-65
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• 2009

Recently, UAV(unmanned aerial vehicle) has evolved into various figure and become miniaturized. On using existing design method, it is hard to make modelling and standardizing design of flight control system of the figure including cylinder like pipe. These problems are caused by uncorrect express of nonlinearity in controller design. Therefore, it is developed through step of correct modelling and simulation on real time sing high efficiency computer in aircraft development of various figure. This is reducing period and expense of aircraft development. For the shake of solving these problems, in-design method has been devised by H.M. Wang. In this paper, an object of control is cylindrical UAV instead of the general figure of aircraft. It was analyzed flight condition, specification about level flight of the UAV and was presented algorithm to find control value.

• Journal of KIISE:Information Networking
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• v.33 no.2
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• pp.113-130
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• 2006

Recently with the explosive growth of Internet applications, the attacks of hackers on network are increasing rapidly and becoming more seriously. Thus information security is emerging as a critical factor in designing a network system and much attention is paid to Network Intrusion Detection System (NIDS), which detects hackers' attacks on network and handles them properly However, the performance of current intrusion detection system cannot catch the increasing rate of the Internet speed because most of the NIDSs are implemented by software. In this paper, we propose a new high performance network intrusion using Network Processor. To achieve fast packet processing and dynamic adaptation of intrusion patterns that are continuously added, a new high performance network intrusion detection system using Intel's network processor, IXP1200, is proposed. Unlike traditional intrusion detection engines, which have been implemented by either software or hardware so far, we design an optimized architecture and algorithms, exploiting the features of network processor. In addition, for more efficient detection engine scheduling, we proposed task allocation methods on multi-processing processors. Through implementation and performance evaluation, we show the proprieties of the proposed approach.

• Journal of KIISE:Information Networking
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• v.31 no.3
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• pp.335-346
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• 2004

In this paper, we present a high-performance fault-tolerant switching networks using a deflection self-routing scheme, and present fault-diagnosis method for the network. We use the facts: 1) Each stage of the Banyan network is arrayed as the sequences of a Cyclic group of SEs. 2) There is the homomorphism between adjacent stages from a view of self-routing, so that all of each Cyclic group is the subgroup of the Cyclic group in the next stage, and there are factor groups due to such subgroup and homomorphism. We provide high-performance fault-tolerant switching networks of which the all links including augmented links are used as the alternate links detouring faulty links. We also present the fault diagnosis scheme for the proposed switching network that provide multiple paths for each input-output pair.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.4
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• pp.401-407
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• 2000

Modern microprocessors exploit instruction-level parallel processing to increase the performance. Especially VLIW processors supported by the parallelizing compiler are used more and more in specific applications such as high-end DSP and graphic processing. Bus-based VLIW architecture was proposed for these specific applications and it was designed to reduce the overhead of forwarding unit and the instruction width. In this paper, a optimizing scheduling compiler developed for the proposed bus-based VLIW processor is introduced. First, the method to model interconnections between buses and resource usage patterns is described. Then, on the basis of the modeling, machine-dependent optimization techniques such as bus-to-register promotion, copy coalescing and operand substitution were implemented. Optimization techniques for general-purpose VLIW microprocessors such as selective scheduling and enhanced pipelining scheduling(EPS) were also implemented. The experiment result shows about 20% performance gain for multimedia application benchmarks.

• Journal of the Korean Chemical Society
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• v.42 no.4
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• pp.416-421
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• 1998

In the reversed-phase ion-pair high performance liquid chromatographic (RPIP-HPLC) elution behavior of noble metal-thiacrown ether complexes, the effects of the concentration of ion-pairing reagent and kind of ligands were studied. It was found that the less the number of atoms in the ring of the thiacrown ether molecule was, the larger the selectivity was, and the elution mechanism of the complexes was explained due to the formation of ion-pair when the concentration of sodium dodecyl sulfate (SDS) in mobile phase was lower than 10 mM and due to the formation of micelle when the SDS concentration was higher than 10 mM. As a conclusion, separations of the noble metal-thiacrown ether complexes in an optimum separation condition were accomplished successfully and the method was proved to be an useful one for the separation and determination of Ag (Ⅰ) ion in a black-white photographic fixing solution.