• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.11
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• pp.2062-2068
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• 2006

In his paper, embedded system implementation for IEEE802.l1p based OFDM-DSRC is presented. After the IEEE802.11p physical layer specification is introduced and BER performance of the modem is evaluated by simulation, implementation aspects of the system such as system architecture, design method and implementation results are addressed. Implemented embedded system for the OFDM-DSRC communication consists of FPGA, flash memory, ARM9 CPU Core, peripherals, etc. from the results, it is shown that the implemented system operates well according to IEEE802.11p specification. It is expected that implemented embedded system shall be used for wireless communication system such as ITS application by enhancing system optimizing.

• Journal of KIISE:Computing Practices and Letters
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• v.5 no.5
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• pp.639-650
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• 1999

Generally, a performance management consists of the iterative process of performance monitoring, performance analysis, and performance tuning. In this paper, we describe the design and implementation of performance monitor and performance tuner which can be used on the top of SPAX, also known as TICOM IV. SPAX has a hierarchical structure. All nodes, each of which has a local memory, are connected to the interconnection network and constructed to form clusters. Therefore, it is necessary to develop a new performance monitor reflecting the underlying hierarchical structure of SPAX, to implement performance monitoring more effectively. Implemented performance monitor can monitor the state of nodes, clusters, and total system of SPAX at realtime. And, implemented performance tuner can change the value of variables related to the performance of SPAX. System manager can perform an effective performance management by using the proposed performance management tools.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.292-303
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• 2010

On-chip cache memories play an important role in both performance and energy consumption points of view in resource-constrained embedded systems by filtering many off-chip memory accesses. We propose a 2-level data cache architecture with a low energy-delay product tailored for the embedded systems. The L1 data cache is small and direct-mapped, and employs a write-through policy. In contrast, the L2 data cache is set-associative and adopts a write-back policy. Consequently, the L1 data cache is accessed in one cycle and is able to provide high cache bandwidth while the L2 data cache is effective in reducing global miss rate. To reduce the penalty of high miss rate caused by the small L1 cache and power consumption of address generation, we propose an ECP(Early Cache hit Predictor) scheme. The ECP predicts if the L1 cache has the requested data using both fast address generation and L1 cache hit prediction. To reduce high energy cost of accessing the L2 data cache due to heavy write-through traffic from the write buffer laid between the two cache levels, we propose a one-way write scheme. From our simulation-based experiments using a cycle-accurate simulator and embedded benchmarks, the proposed 2-level data cache architecture shows average 3.6% and 50% improvements in overall system performance and the data cache energy consumption.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.748-751
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• 2004

In this paper, we discuss about wireless Internet security. The past few years have seen unprecedented growth in the number of wireless user, applications, and network access technologies. Wireless Internet is similar to wired internet, but it has some constrained wireless environment. So many internet technologies for wireless are developing now. There are WAP(Wireless Application Protocol) and WPKI. WAP(now version 2.0) is a protocol specification for wireless communication networks. it provides an application framework and network protocols for wireless devices such as mobile telephones, PDAs and internet technologies. In this paper some analysis of security(e.g. digital signature or encryption) for wireless internet are performed.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2421-2434
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• 1998

This paper describes the design and implementation of performance monitor which can be used at SPAX that is developed to TICOM IV. SPAX has a hierarchical structure, at which nodes which have a local memory, are connected to lnterconnect network and constructed to clusters. So, to do effectivel performance monitorng at SPAX, new monitor is designed, which can monitor the state of node, cluster, and total system of SPAX.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.4
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• pp.378-388
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• 2008

Flash memory has been attracting attention as the next mass storage media for mobile computing systems such as notebook computers and UMPC(Ultra Mobile PC)s due to its low power consumption, high shock and vibration resistance, and small size. A storage system with flash memory excels in random read, sequential read, and sequential write. However, it comes short in random write because of flash memory's physical inability to overwrite data, unless first erased. To overcome this shortcoming, we propose an SSD(Solid State Disk) architecture with two novel features. First, we utilize non-volatile FRAM(Ferroelectric RAM) in conjunction with NAND flash memory, and produce a synergy of FRAM's fast access speed and ability to overwrite, and NAND flash memory's low and affordable price. Second, the architecture categorizes host write requests into small random writes and large sequential writes, and processes them with two different buffer management, optimized for each type of write request. This scheme has been implemented into an SSD prototype and evaluated with a standard PC environment benchmark. The result reveals that our architecture outperforms conventional HDD and other commercial SSDs by more than three times in the throughput for random access workloads.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.4 s.310
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• pp.74-86
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• 2006

This paper proposes a robust and computationally efficient algorithm for automatic video object segmentation. For implementing the spatio-temporal segmentation, which aims for efficient combination of the motion segmentation and the color segmentation, an SOM-based hierarchical clustering method in which the segmentation process is regarded as clustering of feature vectors is employed. As results, problems of high computational complexity which required for obtaining exact segmentation results in conventional video object segmentation methods, and the performance degradation due to noise are significantly reduced. A measure of motion vector reliability which employs MRF-based MAP estimation scheme has been introduced to minimize the influence from the motion estimation error. In addition, a noise elimination scheme based on the motion reliability histogram and a clustering validity index for automatically identifying the number of objects in the scene have been applied. A cross projection method for effective object tracking and a dynamic memory to maintain temporal coherency have been introduced as well. A set of experiments has been conducted over several video sequences to evaluate the proposed algorithm, and the efficiency in terms of computational complexity, robustness from noise, and higher segmentation accuracy of the proposed algorithm have been proved.

• Journal of Broadcast Engineering
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• v.26 no.4
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• pp.429-440
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• 2021

With the recent development of deep convolutional neural network learning, deep learning techniques applied to single image super-resolution are showing good results. One of the existing deep learning-based super-resolution techniques is RDN(Residual Dense Network), in which the initial feature information is transmitted to the last layer using residual dense blocks, and subsequent layers are restored using input information of previous layers. However, if all hierarchical features are connected and learned and a large number of residual dense blocks are stacked, despite good performance, a large number of parameters and huge computational load are needed, so it takes a lot of time to learn a network and a slow processing speed, and it is not applicable to a mobile system. In this paper, we use the residual dense structure, which is a continuous memory structure that reuses previous information, and the residual dense channel attention block using the channel attention method that determines the importance according to the feature map of the image. We propose a method that can increase the depth to obtain a large receptive field and maintain a concise model at the same time. As a result of the experiment, the proposed network obtained PSNR as low as 0.205dB on average at 4× magnification compared to RDN, but about 1.8 times faster processing speed, about 10 times less number of parameters and about 1.74 times less computation.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.9
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• pp.991-998
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• 2014

Embedded System operates hardware installed like processor, memory device, various input/output devices and software to control them. This thesis presents MPU module and Base board which are efficient industrial control through design and manufacture as developing S5PV210 CPU of SAMSUNG used by ARM Cortex-A8 based on Android which is Open mobile platform is installed to embedded system. Data for temperature and humidity which are received by CAN communication module proved the suitability and validity for the embedded platform design as implementing application program employed the native App with Linux Kernel based on the Android OS and application of HTML5.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.30 no.7
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• pp.144-149
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• 2002

This paper presents a technique for real time multiprocessor parallel processing to develop an avionic system computer(ASC) which integrates the avionics control, navigation and fire control, cursive and raster graphic symbol generation into one line replaceable unit. The proposed method has optimal performance by adopting a logically asymmetric structure between four 32bit RISC processors based on the master-slave multiprocessing, a tightly coupled interaction level with the time shared common bus and global memory, and an efficient bus arbitration algorithm. The ASC has been verified through a series of flight tests. The relevant tests also have been rigorously conducted on the prototype ASC such as electrical test, environmental test, and electromagnetic interference test.