• Title/Summary/Keyword: 게이트 커패시턴스

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An Accuracy Improvement Method for the Analysis of Process Variation Effect on CNTFET-based Circuit Performance (CNTFET 기반 회로 성능의 공정 편차 영향 분석을 위한 정확도 향상 방법)

  • Cho, Geunho
    • Journal of IKEEE
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    • v.22 no.2
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    • pp.420-426
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    • 2018
  • In the near future, CNTFET(Carbon NanoTube Field Effect Transistor) is considered as one of the most promising candidate for the replacement of modern silicon-based transistors by utilizing the ballistic or near-ballistic transport capability of CNT(Carbon NanoTube). For the large-scale fabrication of high performance CNTFET, semiconducting CNTs have to be well-aligned with a fixed pitch and high densities in the each CNTFET. However, due to the immaturity of the CNTFET fabrication process, CNTs can be unevenly positioned in a CNTFET and existing HSPICE library file cannot support the circuit level evaluation of performance variation caused by the unevenly positioned CNTs. To evaluate the performance variation, linear programming methodology was suggested previously, but the errors can be made during the calculation of the current and the gate capacitance of a CNTFET. In this paper, the reasons causing errors will be discussed in detail and the new methodology to reduce the errors will be also suggested. Simulation results shows that the errors can be reduced from 7.096% to 3.15%.

Test Generation for Multiple Line Affecting Crosstalk Effect (다중 전송선에 영향을 받는 Crosstalk 잡음을 위한 테스트 생성)

  • Lee, Young-Gyun;Yang, Sun-Woong;Kim, Moon-Joon;Chang, Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.9
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    • pp.28-36
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    • 2002
  • As cross-coupling capacitance generated in transmission line has been an important issue in VLSI world, a couple of ATPG algorithms has been proposed. However they were studied only for a simple single-line effect problem, so it cost so much time for an unsatisfying test generation efficiency. In this paper, we studied a noise model for multiple affected lines and generated test patterns in a short time. This paper proposes a crosstalk model affected by multiple tranmission lines and implemented an ATPG algorithm for detection of crosstalk noise faults. We modeled the crosstalk noise by multiple transmission line and made a truth table for this. We implemented an ATPG algorithm based on PODEM and revealed the results.

Silicon Nano wire Gate-all-around SONOS MOSFET's analog performance by width and length (실리콘 나노와이어 MOSFET's의 채널 길이와 폭에 따른 아날로그 특성)

  • Kwon, Jae-hyup;Seo, Ji-hoon;Choi, Jin-hyung;Park, Jong-tae
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.10a
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    • pp.773-776
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    • 2014
  • In this work, analog performances of silicon nanowire MOSFET with different length and channel width have been measured. The channel widths are 20nm, 30nm, 80nm, 130nm and lengths are 250nm, 300nm, 350nm, 500nm. temperatures $30^{\circ}C$, $50^{\circ}C$, $75^{\circ}C$, $100^{\circ}C$ have been measured. The trans-conductance, early voltage, gain, drain current and mobility have been characterized as a function of temperature. The mobility has been enhanced with wider channel width but it has been reduced with longer length and higher temperature. The trans-conductance has been increased with wider channel width. The early voltage has been enhanced with increase of gate length and temperature but it has been reduced with wider width. Therefore, gain has been enhanced with increase of gate longer length and wider width but it has been reduced with higher temperature.

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Circuit Modeling and Simulation of Active Controlled Field Emitter Array for Display Application (디스플레이 응용을 위한 능동 제어형 전계 에미터 어레이의 회로 모델링 및 시뮬레이션)

  • Lee, Yun-Gyeong;Song, Yun-Ho;Yu, Hyeong-Jun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.2
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    • pp.114-121
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    • 2001
  • A circuit model for active-controlled field emitter array(ACFEA) as an electron source of active-controlled field emission display(ACFED) has been proposed. The ACFEA with hydrogenated amorphous silicon thin-film transistor(a-Si:H TFT) and Spindt-type molibdenum tips (Spindt-Mo FEA) has been fabricated monolithically on the same glass. A-Si:H TFT is used as a control device of field emitters, resulting in stabilizing emission current and lowering driving voltage. The basic model parameters extracted from the electrical characteristics of the fabricated a-Si:H TFT and Spindt-Mo FEA were implemented into the ACFEA model with a circuit simulator SPICE. The accuracy of the equivalent circuit model was verified by comparing the simulated results with the measured one through DC analysis of the ACFEA. The transient analysis of the ACFEA showed that the gate capacitance of FEA along with the drivability of TFT strongly affected the response time. With the fabricated ACFEA, we obtained a response time of 15$mutextrm{s}$, which was enough to make 4bit/color gray scale with the pulse width modulation (PWM).

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