• Title/Summary/Keyword: 게이트 시뮬레이션

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Overhead Reduction Methods in Communication between 6LoWPAN and External Node (6LoWPAN 노드와 외부 노드의 통신 시에 오버헤드 감소 방법)

  • Choi, Dae-In;Enkhzul, Doopalam;Park, Jong-Tak;Kahng, Hyun-K.
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.5B
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    • pp.437-442
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    • 2011
  • As an Internet Engineering Task Force (IETF) Working Group, 6LoWPAN is standardizing the IPv6 packet transfer technology in accordance with IEEE 802.15.4. It has completed two Request for Comments (RFC) documents, one of which, RFC 4944, addresses fragmentation, reassembly, and header compression technologies. In this paper, a communication mechanism is proposed to provide efficient communication between 6LoWPAN and external nodes. In this mechanism, the gateway between 6LoWPAN and external networks serves as the proxy gateway between nodes. The simulation was conducted using QualNet to compare the performance of the proposed mechanism and the existing RFC 4944 method. The comparative analysis of the proposed mechanism and the existing method showed that the proposed method performed better.

Analysis of Channel Doping Profile Dependent Threshold Voltage Characteristics for Double Gate MOSFET (이중게이트 MOSFET에서 채널도핑분포의 형태에 따른 문턱전압특성분석)

  • Jung, Hak-Kee;Han, Ji-Hyung;Lee, Jae-Hyung;Jeong, Dong-Soo;Lee, Jong-In;Kwon, Oh-Shin
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.6
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    • pp.1338-1342
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    • 2011
  • In this paper, threshold voltage characteristics have been analyzed as one of short channel effects occurred in double gate(DG)MOSFET to be next-generation devices. The Gaussian function to be nearly experimental distribution has been used as carrier distribution to solve Poisson's equation, and threshold voltage has been investigated according to projected range and standard projected deviation, variables of Gaussian function. The analytical potential distribution model has been derived from Poisson's equation, and threshold voltage has been obtained from this model. Since threshold voltage has been defined as gate voltage when surface potential is twice of Fermi potential, threshold voltage has been derived from analytical model of surface potential. Those results of this potential model are compared with those of numerical simulation to verify this model. As a result, since potential model presented in this paper is good agreement with numerical model, the threshold voltage characteristics have been considered according to the doping profile of DGMOSFET.

Development of Mobile Volume Visualization System (모바일 볼륨 가시화 시스템 개발)

  • Park, Sang-Hun;Kim, Won-Tae;Ihm, In-Sung
    • Journal of KIISE:Computing Practices and Letters
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    • v.12 no.5
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    • pp.286-299
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    • 2006
  • Due to the continuing technical progress in the capabilities of modeling, simulation, and sensor devices, huge volume data with very high resolution are common. In scientific visualization, various interactive real-time techniques on high performance parallel computers to effectively render such large scale volume data sets have been proposed. In this paper, we present a mobile volume visualization system that consists of mobile clients, gateways, and parallel rendering servers. The mobile clients allow to explore the regions of interests adaptively in higher resolution level as well as specify rendering / viewing parameters interactively which are sent to parallel rendering server. The gateways play a role in managing requests / responses between mobile clients and parallel rendering servers for stable services. The parallel rendering servers visualize the specified sub-volume with rendering contexts from clients and then transfer the high quality final images back. This proposed system lets multi-users with PDA simultaneously share commonly interesting parts of huge volume, rendering contexts, and final images through CSCW(Computer Supported Cooperative Work) mode.

Instruction-level Power Model for Asynchronous Processor (명령어 레벨의 비동기식 프로세서 소비 전력 모델)

  • Lee, Je-Hoon
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.7
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    • pp.3152-3159
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    • 2012
  • This paper presents the new instruction-level power model for an asynchronous processor. Until now, the various power models for estimating the power dissipation of embedded processor in SoC are proposed. Since all of them are target to the synchronous processors, the accuracy is questionable when we apply those power models to the asynchronous processor in SoC. To solve this problem, we present new power model for an asynchronous processor by reflecting the behavioral features of an asynchronous circuit. The proposed power model is verified using an implementation of asynchronous processor, A8051. The simulation results of the proposed model is compared with the measurement result of gate-level synthesized A8051. The proposed power model shows the accuracy of 90.7% and the simulation time for estimation the power consumption was reduced to 1,900 times.

Design of Extendable BCD-EXCESS 3 Code Convertor Using Quantum-Dot Cellular Automata (확장성을 고려한 QCA BCD-3초과 코드 변환기 설계)

  • You, Young-won;Jeon, Jun-cheol
    • Journal of Advanced Navigation Technology
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    • v.20 no.1
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    • pp.65-71
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    • 2016
  • Quantum-dot cellular automata (QCA) consists of nano-scale cells and demands very low power consumption so that it is one of the alternative technologies that can overcome the limits of scaling CMOS technologies. Typical BCD-EXCESS 3 code converters using QCA have not considered the scalability so that the architectures are not suitable for a large scale circuit design. Thus, we design a BCD-EXCESS 3 code converter with scalability using QCADesigner and verify the effectiveness by simulation. Our structure have reduced 32 gates and 7% of garbage space rate compare with typical URG BCD-EXCESS 3 code converter. Also, 1 clock is only needed for circuit expansion of our structure though typical QCA BCD-EXCESS 3 code converter demands 7 clocks.

Analysis of subthreshold region transport characteristics according to channel thickness for DGMOSFET (DGMOSFET의 채널두께에 따른 문턱전압이하영역에서의 전송특성분석)

  • Han, Ji-Hyung;Jung, Hak-Kee;Lee, Jong-In;Jeong, Dong-Soo;Kwon, Oh-Shin
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.10a
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    • pp.737-739
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    • 2010
  • In this paper, the subthreshold characteristics have been alanyzed using MicroTec4.0 for double gate MOSFET(DGMOSFET). The technology for characteristic analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high-integrated device by computer simulation and fabricate the device having such characteristics became one of very important subjects. The oxide thickness and channel thickness in DG MOSFET determines threshold voltage and extensively influences on Ss(Subthreshold swing). We have investigated the threshold voltage and Ss(Subthreshold swing) characteristics according to variation of channel thickness from 1nm to 3nm in this study.

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The Impact of traps on the DC Characteristics of AlGaN/GaN HEMT (AlGaN/GaN HEMT의 트랩에 의한 DC 출력 특성 전산모사)

  • Jung, Kang-Min;Kim, Su-Jin;Kim, Jae-Moo;Kim, Dong-Ho;Lee, Young-Soo;Choi, Hong-Goo;Hahn, Cheol-Koo;Kim, Tae-Geun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.76-76
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    • 2008
  • 갈륨-질화물(GaN) 기반의 고속전자이동도 트랜지스터(high electron mobility transistor, HEMT)는 최근 마이크로파 또는 밀리미터파 등의 고주파 대역의 통신시스템에 널리 사용되는 전자소자이자, 차세대 고주파용 전력 소자로 각광받고 있다. AlGaN/GaN HEMT에서 AlGaN층과 GaN층의 이종접합 구조(heterostructure)는 두 물질 간의 큰 전도대의 불연속성으로 인해 발생하는 이차원 전자가스(two-dimensional electron gas, 2DEG) 채널을 이용하여 높은 전자이동도, 높은 항복전압 및 우수한 고출력 특성을 얻는 것이 가능하다. 그러나 이린 이론적인 우수한 특성에도 불구하고 실제 AlGaN/GaN HEMT 소자에서는 AlGaN 표면과 AlGaN과 GaN 층 사이 접합면, AlGaN과 GaN 벌크층에 존재하는 트랩의 영향으로 이론보다 낮은 DC 출력 특성을 갖는다. 본 논문에서는 표면, 접합면, 벌크 층에 존재하는 트랩들을 각각의 존재 유무에 따라 시뮬레이션 함으로써 각각의 트랩이 DC 특성에 미치는 영향에 대해서 알아본다. 또한 소스와 게이트, 드레인과 게이트간의 거리에 따라 표면 트랩에 따른 영향과 AlGaN층과 GaN 층의 두께를 변화시켜가면서 각 층의 두께에 따라 벌크 트랩이 DC 특성에 미치는 영향을 알아보았다. 본 논문에서 트랩에 따른 특성의 파악을 위해서 $ATLAS^{TM}$를 이용하여 전산모사 하였다.

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Design of a Distributed Mixer Using Dual-Gate MESFET's (Dual-Gate MESFET를 이용한 분포형 주파수 혼합기의 설계)

  • Oh, Yang-Hyun;An, Jeong-Sig;Kim, Han-Suk;Lee, Jong-Arc
    • Journal of IKEEE
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    • v.2 no.1 s.2
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    • pp.15-23
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    • 1998
  • In this paper, distributed mixer is studied at microwave frequency. The circuit of distributed mixer composed of gate 1,2, drain transmission lines, matching circuits in input and output terminal, DGFET's. For impedance matching of input and output port at higher frequency, image impedance concept is introduced. In distributed mixer, a DGFET's impedances are absorbed by artificial transmission line, this type of mixer can get a very broadband characteristics compared to that of current systems. A RF/LO signal is applied to each gate input port, and are excited the drain transmission line through transcondutance of the DGFET's. The output signals from each drain port of DGFET's added in same phases. We designed and frabricated the distributed mixer, and a conversion gain, noise figure, bandwidth, LO/RF isolation of the mixer are shown through computer simulation and experimentation.

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An Analytical DC Model for HEMT's (헴트 소자의 해석적 직류 모델)

  • Kim, Young-Min
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.6
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    • pp.38-47
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    • 1989
  • A purely analytical model for HEMT's based on a two dimensional charge control simul-ation[4] is proposed. In this model proper treatment of diffusion effect of electron transport along a 2-DEG (two dimensional electron gas) channel is perfoemed. This diffusion effect is shown to effectively increase the bulk mibility and threshold voltage of the I-V curves compared to the existing models. The channel thickness and gate capacitance are expressed as functions of gate voltages covering subthreshold characteristics of HEMT's analytically. By introducing the finite channel opening and an effiective channel-length modulation, the solpe of the saturation region of the I-V curves ws modeled. The smooth transition of the I-V curves at linear-to-saturation regions of the I-V curves was possible using the continuous Troffimenkoff-type of field dependent mobility. Furthermore, a correction factor f was introduced to account for the finite transition section forming between a GCA and a saturated section. This factor removes large discrepancies in the saturation region of the I-V curve predicted by existing l-dimensional models.

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LOSIM : Logic Simulation Program for VLSI (LOSIM : VLSI의 설계검증을 위한 논리 시뮬레이션 프로그램)

  • Kang, Min-Sup;Lee, Chul-Dong;Yu, Young-Uk
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.5
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    • pp.108-116
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    • 1989
  • The simulator described here-LOSIM(LOgic SIMulator)-was developed to verify the logic design for VLSI(Very Large Scale Integrated) circuits at mixed level. In this paper, we present a modeling approach to obtain more accurate results than conventional logic simulators [5-6,9] for general elements, functional elements, transmission gates and tri-state gates using eight signal values and two gignal strengths. LOSIM has the capability which can perform timing and hazard analysis by using assignable rise and fall delays. We also prosent an efficient algorithm to accurately detectdynamic and static hazards which may be caused by the circuit delays. Our approach is based on five logic values and the scheduled time. LOSIM has been implemented on a UN-3/160 workstation running Berkeley 4.2 UNIX, and the program is written in C language. Static RAM cell and asynchronous circuit are illustrated as an example.

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