• Journal of the Korea Society of Computer and Information
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• v.18 no.10
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• pp.13-21
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• 2013

Recently, although the number of cores on a chip multi-processor increases, multi-programming or multi-threaded programming techniques to utilize the whole cores are still insufficient. Therefore, there inevitably exist some idle cores which are not working. This results in a waste of the caches, so-called idle caches which are dedicated to those idle cores. In this research, we propose amethodology to exploit idle caches effectively as victimcaches of on-chip memory resource. In simulation results, we have achieved 19.4%and 10.2%IPC improvement in 4-core and 16-core respectively, compared to previous technique.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.697-699
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• 2001

가상환경에서의 실시간 상호작용을 지원하기 위해 가상세계의 데이터를 서버에서 클라이언트로 복제 해놓는 방법이 쓰여지고 있다. 효과적인 복제를 위해서는 두 가지 기법 - 우선 순위기반의 객체 전송과 캐싱 및 프리패칭 기법이 쓰이고 있다. 기존의 캐시와 프리패칭 기법들은 사용자와 객체간의 지역적 관계를 이용하고 있지만, 이는 어떤 종류의 객체가 사용자에게 더 중요한 지를 결정할 수 없는 단점이 있다. 본 연구에서는 지역적 관계 뿐 아니라 개별 사용자의 객체에 대한 관심도로부터 발생하는 객체에 대한 우선 순위를 이용하여 사용자 기반의 캐싱과 프리패칭을 사용하는 분산 가상환경 하에서의 확장성 있는 데이터 관리 기법을 제안한다. 또한 이 기법에서는 사용자의 행동 모드를 구분함으로써 더욱 높은 캐시 적중 비율을 얻을 수 있다.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.1_2
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• pp.15-34
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• 2006

This paper introduces an empirical modeling technique. This technique uses a set of sample results which are collected from a few small scale simulations. Empirical models are developed by applying a couple of statistical estimation techniques to these samples. We built two types of models for cache miss rates in Symmetric Multiprocessor systems. One is for the changes of input data set size while the specification of target system is fixed. The other is for the changes of the number of processors in target system while the input data set size is fixed. To develop accurate models, we built individual model for every kind of cache misses for each shared data structure in a program. The final model is then obtained by integrating them. Besides, combined use of Least Mean Squares and Robust Estimations enhances the quality of models by minimizing the distortion due to outliers. Empirical modeling technique produces extremely accurate models without analysis on sample data. In addition, since only snail scale simulations are necessary, once a set of samples can be collected, empirical method can be adopted in any research areas. In 17 cases among 24 trials, empirical models present extremely low prediction errors below $1\%$. In the remaining cases, the accuracy is excellent, as well. The models sustain high quality even when the behavioral characteristics of programs are irregular and the number of samples are barely enough.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.619-621
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• 2002

90년대 중반에 등장한 그리드(GRID)는 지역적으로 분산되어 있으며 소유자가 서로 다른 다양한 컴퓨팅 자원의 효과적인 공유를 목적으로 하며, 시스템의 구축에 필요한 스케쥴링, 자원 관리, 보안, 성능 측정 및 상태 모니터링 등의 문제를 해결하기 위한 다양한 미들웨어 및 개발 도구가 연구되고 있다. 그리드 시스템에서 사용되는 데이터는 FTP 서버, 파일 시스템, 데이터베이스 등 여러 장치에 저장되어 개별적인 인터페이스를 통해 접근된다. 각각의 인터페이스론 통하여 접근하므로 사용 방법이 어렵고 확장성이 떨어지는 단점이 있다. 이러한 문제점을 해결하기 위하여, 본 연구에서는 데이터베이스, FTP, 파일 시스템에 산재한 그리드 데이터를 동시에 지원하고, URL을 통해 단일 인퍼페이스로 접근하게 해 주며, 3계층 구조와 데이터 캐시를 이용하여 성능과 확장성을 제공하는 시스템을 구현한다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2014.07a
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• pp.333-335
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• 2014

페이스북, 트위터와 같은 클라우드 및 웹 서비스 제공회사와 클라우드 및 웹 서비스 제공자는 수많은 사용자들에 의해 발생되는 무수한 데이터를 빠르게 처리하기 위해 하드 디스크보다는 램에 저장 할 필요가 있다. 그러한 좋은 도구로서 분산메모리 객체 캐싱 소프트웨어인 멤캐시드가 있다. 멤캐시드의 성능은 저장공간의 크기에 따라 많은 차이를 보이는데, 하드웨어의 비용, 전력소비와 온도조절 등 공간의 제약을 감안했을 때, 무작정 개별 서버에 많은 RAM을 장착하거나, 서버 배열을 확장하는 것은 효율적인 방법이 아니다. 따라서 많은 양의 데이터가 메모리에 저장이 가능하도록 RAM과 SSD를 같이 확장한 SSD 기반 하이브리드 메모리를 제안한다. 하이브리드 메모리는 객체 캐시로 동작하고 페이지 단위로 할당하는 것보다 객체 단위로 자원할당을 함으로서 SSD에서 빠른 무작위 읽기를 할 수 있게 해 객체의 접근속도를 향상시켰다.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.113-124
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• 2009

With increasing multicore system, much effort has been put on the performance improvement of its application. Because multicore system has multiple processing devices in one system, its processing power increases compared to the single core system. However in many cases the advantages of multicore can not be exploited fully because the existing software and hardware were designed to be suitable for single core. When the existing software runs on multicore, its performance improvement is limited by the bottleneck of sharing resources and the inefficient use of cache memory on multicore. Therefore, according as the number of core increases, it doesn't show performance improvement and shows performance drop in the worst case. In this paper we propose a method of performance improvement of multicore system by applying Flow-Level Parallelism to the existing TCP/IP network application and operating system. The proposed method sets up the execution environment so that each core unit operates independently as much as possible in network application, TCP/IP stack on operating system, device driver, and network interface. Moreover it distributes network traffics to each core unit through L2 switch. The proposed method allows to minimize the sharing of application data, data structure, socket, device driver, and network interface between each core. Also it allows to minimize the competition among cores to take resources and increase the hit ratio of cache. We implemented the proposed methods with 8 core system and performed experiment. Experimental results show that network access speed and bandwidth increase linearly according to the number of core.

• The KIPS Transactions:PartC
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• v.16C no.4
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• pp.417-422
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• 2009

Implementation of DPI(Deep Packet Inspection) system on a general purpose multiprocessor platform is an attractive option from the implementation cost point of view, since it does not require high-cost customized hardware. Load balancing has been considered as a primary means to achieve high performance in multi processor systems. We claim, however, that in case of DPI system design simply balancing the load of each processor does not necessarily yield the highest system performance. Instead, we propose a method in which tasks are allocated to processors based on their functions. We implemented the proposed method in dual processor Linux system and compare its performance with the existing load balancing methods. Under the proposed method, one processor is dedicated to deal with interrupt handling and generic packet processing, while another processor is dedicated to DPI processing. According to experimental results, the proposed scheme outperforms the existing schemes by 60%, mainly because of the reduction of cache miss and spin lock occurrences.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.2
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• pp.75-85
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• 2014

Recently, mobile SNS traffic has increased tremendously due to the deployment of smart devices such as smart phones and smart tablets. In this paper, mobile integrated SNS gateway is proposed to cope with massive SNS traffic. Most of mobile SNS applications update the information with individual connection to the corresponding servers. The proposed gateway integrates these applications. It is for reducing SNS traffic caused by continuous data request and improving the mobile communication performance. The key elements of the mobile integrated SNS gateway are the synchronization, cache and integrated certification. The proposed protocol and gateway system have implemented on the testbed which deployed on the real network to evaluate the performance of the proposed gateway. Finally, we present the caching performance of gateway system implementation.