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Empirical Modeling for Cache Miss Rates in Multiprocessors  

Lee, Kang-Woo (동국대학교 정보통신공학과)
Yang, Gi-Joo (동국대학교 정보통신공학과)
Park, Choon-Shik (동국대학교 정보통신공학과)
Publication Information
Journal of KIISE:Computer Systems and Theory / v.33, no.1_2, 2006 , pp. 15-34 More about this Journal
Abstract
This paper introduces an empirical modeling technique. This technique uses a set of sample results which are collected from a few small scale simulations. Empirical models are developed by applying a couple of statistical estimation techniques to these samples. We built two types of models for cache miss rates in Symmetric Multiprocessor systems. One is for the changes of input data set size while the specification of target system is fixed. The other is for the changes of the number of processors in target system while the input data set size is fixed. To develop accurate models, we built individual model for every kind of cache misses for each shared data structure in a program. The final model is then obtained by integrating them. Besides, combined use of Least Mean Squares and Robust Estimations enhances the quality of models by minimizing the distortion due to outliers. Empirical modeling technique produces extremely accurate models without analysis on sample data. In addition, since only snail scale simulations are necessary, once a set of samples can be collected, empirical method can be adopted in any research areas. In 17 cases among 24 trials, empirical models present extremely low prediction errors below $1\%$. In the remaining cases, the accuracy is excellent, as well. The models sustain high quality even when the behavioral characteristics of programs are irregular and the number of samples are barely enough.
Keywords
Empirical Modeling; Prediction Model; Statistical Estimation Methods; Cache Misses; Symmetric Multiprocessors;
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