• Journal of Teachers' Pension
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• v.3
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• pp.255-278
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• 2018

본 연구는 사학연금에서 연기연금재도의 도입 필요성을 검토하고 특히 도입 시 적용할 가산율 설정 등 구체적인 도입방안을 제시하고자 하였다. 사학연금에서 연기연금제도는 수급자의 근로유인과 활동적 노년의 진작을 위해서 필요하다. 이는 또한 국민연금과 직역연금이 동조화되고 있는 현 추세와도 일치한다. 이 연구는 또한 국민연금의 연기연금제도를 참고하여 보험수리적 중립성에 입각한 공정가산율을 산출하였다. 이 방식에 따르면 사학연금 연기연금제도의 핵심제도인 공정가산율은 6.2%로 나타났다.

• Journal of the Society of Naval Architects of Korea
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• v.33 no.3
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• pp.94-102
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• 1996

An interpretation for the additive and multiplicative decomposition theory of the deformation gradient tensor in finite deformation problems is presented. the conventional methods have not provided the additive deformation velocity gradient. Moreover the plastic deformation velocity gradients are not free from elastic deformations. In this paper, a modified multiplicative decomposition is introduced with the assumption of coaxial plastic deformation velocity gradient. This strategy well gives the additive deformation velocity gradient in which the plastic deformation velocity gradient is not affect4d by the elastic deformation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.7A
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• pp.724-729
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• 2007

In this paper, we consider a joint optimization of transmitter and receiver in additive cyclostationary noise with zero forcing criterion. We assume that the period of the cyclostationary noise is the same as the inverse of the symbol transmission rate and that the noise has a positive-definite autocorrelation function. The data sequence is modeled as a wide-sense stationary colored random process and the channel is modeled as a linear time-invariant system with a frequency selective impulse response. Under these assumptions and a constraint on the average power of the transmitted signal, we derive the optimum transmitter and receiver waveforms that jointly minimizes the mean square error with no intersymbol interference. The simulation results show that the proposed system has a better BER performance than the systems with receiver only optimization and the systems with no transmitter and receiver optimization.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.115-122
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• 2004

In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.1C
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• pp.131-139
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• 2008

This paper presents a scalable dual-field Montgomery multiplier based on a new multi-precision carry save adder(MP-CSA), which operates in both types of finite fields GF(p) and GF($2^m$). The new MP-CSA consists of two carry save adders(CSA). Each CSA is composed of n = [w/b] carry propagation adders(CPA) for a modular multiplication with w-bit words, where b is the number of dual field adders(DFA) in a CPA. The proposed Montgomery multiplier has roughly the same timing complexity compared with the previous result, however, it has the advantage of reduced chip area requirements. In addition, the proposed circuit produces the exact modular multiplication result at the end of operation unlike the previous architecture. Furthermore, the proposed Montgomery multiplier has a high scalability in terms of w and m. Therefore, it can be used to multiplier over GF(p) and GF($2^m$) for cryptographic applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.871-880
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• 1993

Conventional binary addition rules require a carry formation and propagation to the most significant bit, and lead to serial addition. Thus, the carry progapation in a binary addition stands as a hindrance to the full utilization of parallelism optics offers, Optical adders using a modified signed-digit(MSD) number system have been proposed to eliminate the carry propagation chain states to represent the three possible digits of MSD number system must encode three different states to represent the three possible digits of MSD. In the paper, we propose the design of a parallel optical adder based on 2-bit addition rules using the method of symbolic substitution(SS).

• Korean Journal of Poultry Science
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• v.44 no.4
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• pp.253-258
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• 2017

This study was aimed at evaluating the additivity of crude protein digestibility in mixed diets of corn and soybean meal (SBM), and comparing direct and indirect methods for evaluating crude protein (CP) digestibility. Totally, five hundred and twenty-five 18-day-old broiler chickens were grouped into 7 blocks based on body weight, and randomly allocated to 6 treatment groups in a randomized complete block design. The basal diet, diet 3, was corn-SBM-based, containing 65% corn and 28% SBM. Diets 1 and 5 contained corn and SBM, respectively, as the sole CP source. To use the difference method, 2 diets, diets 2 and 4, were prepared by mixing corn and SBM at the expense of the basal diet, respectively. Diet 2 contained 79% corn and 14% SBM, and diet 4 contained 32.5% corn and 34% SBM. To evaluate the additivity of digestibility values, the difference between measured values for the mixed diets (diets 2, 3, and 4) and predicted values calculated using the measured values for diets 1 and 5 was examined. The apparent (AID) and standardized (SID) ileal digestibility of CP in SBM differed between the direct and indirect methods; however, corresponding digestibility did not differ for corn. Additionally, the predicted and measured digestibility of both AID and SID differed in diets 2 and 3, implying that the digestibility values obtained from diets 1 and 5 were not additive for mixed diets. In conclusion, this study showed that digestibility evaluated by direct and indirect methods depends on the ingredients having different CP concentrations, and this finding may be considered to improve the accuracy of feed formulation for broiler chickens.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.183-195
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• 2012

We propose a variable-latency Decimal Floating Point(DFP) adder which adopts the dual data path scheme. It is to speed addition and subtraction of operand that has identical exponents. The proposed DFP adder makes use of L. K. Wang's operand alignment algorithm, but operates through high speed data-path in guaranteed accuracy range. Synthesis results show that the area of the proposed DFP adder is increased by 8.26% compared to the L. K. Wang's DFP adder, though critical path delay is reduced by 10.54%. It also operates at 13.65% reduced path than critical path in case of an operation which has two DFP operands with identical exponents. We prove that the proposed DFP adder shows higher efficiency than L. K. Wang's DFP adder when the ratio of identical exponents is larger than 2%.

• Journal of the Korea Society of Computer and Information
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• v.15 no.2
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• pp.9-18
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• 2010

High performance is required with small size and low power in the mobile embedded system. A CORDIC algorithm can compute transcendental functions effectively with only small adders and shifters and is suitable one for the mobile embedded system. However CORDIC unit has performance degradation according due to iterative inter-rotations. Adder design is an important design unit to be optimized for a high performance and low power CORDIC unit. It is necessary to explore the design space of a CORDIC unit considering trade-offs of an adder unit while satisfying delay, area and power constraints. In this paper, we suggest a CORDIC architecture employing a heterogeneous adder and an optimization methodology for producing better optimal tradeoff points of CORDIC designs.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.