• Title/Summary/Keyword: 가변주파수

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Method for Improving the Usage Efficiency of Frequency in Terrestrial DMB (지상파 DMB에서 주파수 이용 효율을 개선하기 위한 방법)

  • Lee, Gwang-Soon;Lee, Hyun;Bae, Jae-Hwui;Lee, Soo-In
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2010.07a
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    • pp.370-371
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    • 2010
  • 본 논문은 지상파 DMB에서 각 서비스 사업자들을 위해 이미 할당된 주파수 블록(block)들간 가드밴드내에 신규 블록을 추가로 할당함으로써 주파수 이용 효율을 높이기 위한 방법을 제안한다. 본 논문은 특히 6 MHz TV 대역내에 이미 할당되어 서비스 중인 현재의 지상파 DMB 서비스와 역방향 호환성을 유지하면서 주파수 가드밴드 영역을 최대한 활용하기 위해, 종래의 송신 시스템에 새로운 서브캐리어를 삽입하고 단일 6MHz 주파수 대역의 전송신호를 생성하기 위한 방법을 제시하고 있다. 본 논문에서의 제안한 방법을 활용하면, 서비스 사업자 입장에서는 가변적인 주파수 대역폭 이용을 통해 좀 더 다양한 서비스 모델을 구상할 수 있고, 사용자 측면에서는 단말 상황에 따라서 기본적인 서비스부터 고품질의 모바일 멀티미디어 서비스를 제공받을 수 있을 것이다.

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Implementation of an analog front-end for electroencephalogram signal processing (뇌전도 신호 처리용 아날로그 전단부 구현)

  • Kim, Min-Chul;Shim, Jae Hoon
    • Journal of Korea Society of Industrial Information Systems
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    • v.18 no.5
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    • pp.15-18
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    • 2013
  • This paper presents an analog front-end for electroencephalogram(EEG) signal processing. Since EEG signals are typically weak and located at very low frequencies, it is imperative to implement an amplifier with high gain, high common-mode rejection ratio(CMRR) and good noise immunity at very low frequencies. The analog front-end of this paper consists of a programmable-gain instrumentation amplifier and a band-pass filter. A frequency chopping technique is employed to remove the low-frequency noise. The circuits were fabricated in 0.18um CMOS technology and measurements showed that the analog front-end has the maximum gain of 60dB and >100dB CMRR over the programmable gain range.

A Tunable Bandpass $\Sigma-\Delta$ Modulator with Novel Architecture (새로운 구조를 가지는 Tunable Bandpass $\Sigma-\Delta$ Modulator)

  • Kim, Jae-Bung;Cho, Seong-Ik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.135-139
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    • 2008
  • In this paper, tunable SC(switched capacitor) 2nd order bandpass $\Sigma-\Delta$(Sigma-Delta) modulator with novel architecture that can adjust the IF band center frequency by one coefficient value is proposed for data conversion in the IF(Intermediate Frequency) band. Its architecture can optionally adjust all the 2nd order noise transfer function in comparison with the conventional architecture. In order to adjust the center frequency, the conventional architecture needs the two variable coefficient values, basic clock and eight clocks. On the other hand, the proposed architecture can adjust the center frequency by one variable coefficient value and basic clock only.

A study of Voltage Controlled Oscillator Design for 2.45GHz RFID Reader Using CMOS 0.18um Process (CMOS 0.18um 공정을 이용한 2.45GHz 대역 RFID 리더용 전압 제어 발진기 설계 연구)

  • Jung, Hyo-Bin;Ko, Jae-Hyeong;Chang, Se-Wook;Kim, Hyeong-Seok
    • Proceedings of the KIEE Conference
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    • 2008.07a
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    • pp.1399-1400
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    • 2008
  • 본 논문에서는 TSMC 0.18um 공정을 이용하여 2.45GHz 대역에서 동작하는 RFID 리더에 적용 할 수 있는 전압제어 발진기를 설계하였다. 위상 잡음 특성 향상을 위해 PMOS, NMOS 소자를 대칭으로 구성한 complementary cross-coupled LC 발진기 구조로 설계 하였고 MOS 배렉터를 이용하여 주파수를 가변 하였다. 또한 공정에서 사용되는 인덕터에 차폐 도체면(PGS:Patterned Ground Shield) 구조를 삽입했을 때 인덕터의 품질계수가 약 5.82% 향상되었고. 이에 따른 위상 잡음은 1MHz offset 주파수에서 PGS를 삽입하지 않는 구조에서는 -102.666dBc/Hz 이며, PGS 구조를 삽입한 구조는 -104.328dBc/Hz로 약1.662dBc 정도의 성능이 향상 되었다. 전압제어 발진기 Core 사이즈는 900um ${\times}$ 590um이고 주파수 가변 범위는 배렉터 전압 1.2${\sim}$2.1V에서 249MHz로 11.4% 특성을 보였다. 1.8V공급전압에서 5.76mW의 전력소모를 보였다.

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A DLL-Based Frequency Synthesizer for Generation of Various Clocks (가변 클록 발생을 위한 DLL 주파수 합성기)

  • 이지현;송윤귀;최영식;최혁환;류지구
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.6
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    • pp.1153-1157
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    • 2004
  • This paper describes a new programmable DLL_based frequency synthesizer. Generally, PLLs have been used for frequency synthesis. Inherent fast locking DLLs are also used for frequency synthesis. However, DLL needs a frequency multiplier for various frequencies. A conventional frequency multiplier used in DLL has a restriction in which a multiple is fixed. However, the proposed DLL can generate clocks which are from 6 times to 10 times of the reference clock. Frequency range of the proposed DLL is from 600MHz to 1GHz. The idea has been confirmed by HSPICE simulations in a $0.35-\mu\textrm{m}$ CMOS process.

Single-frequency Wavelength Tunable Erbium-doped Fiber Ring Laser (단일 주파수로 발진하는 파장 가변 어븀 첨가 광섬유 링 레이저)

  • Kim, Ryun-Kyung;Chu, Su-Ho;Han, Young-Geun
    • Korean Journal of Optics and Photonics
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    • v.21 no.5
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    • pp.185-189
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    • 2010
  • We demonstrate a single-frequency wavelength tunable erbium-doped fiber (EDF) ring laser. We used an unpumped-EDF as a saturable-absorber in order to obtain a stable single-frequency with a narrow-linewidth single-polarization mode in the ring cavity. The lasing wavelength was controlled by using bending-induced strain, such as tension and compression strain corresponding to the bending direction, applied to the fiber gratings. The fiber laser exhibited an output power of -1.85 dBm at a wavelength of 1540.72 nm for a pumping power of ~400 mW. An extinction ratio was measured to be more than 60 dB. The proposed tunable fiber laser maintains nearly the same output power while its lasing wavelength is controlled over in a wavelength range of 5 nm.

Design of Programmable Baseband Filter for Direct Conversion (Direct Conversion 방식용 프로그래머블 Baseband 필터 설계)

  • Kim, Byoung-Wook;Shin, Sei-Ra;Choi, Seok-Woo
    • Journal of Korea Multimedia Society
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    • v.10 no.1
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    • pp.49-57
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    • 2007
  • Recently, CMOS RF integration has been widely explored in the wireless communication area to save cost, power, and chip area. The direct conversion architecture, rather than a more conventional super-het-erodyne, has been an attractive choice for single-chip integration because of its many advantages. However, the direct conversion architecture has several fundamental problems to solve in achieving performance comparable to a super-heterodyne counterpart. In this paper, we describe a programmable filter for mobile communication terminals using a direct conversion architecture. The proposed filter can be implemented with the active-RC filter and programmed to meet the requirements of different communication standards, including GSM, DECT and WCDMA. The filter can be tuned to select a detail frequency by changing the gate voltage of the MOS resistors. The gain of the proposed architecture can be programmed from 27dB to 72dB using the filter gain and VGA in 3dB steps.

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Design and Fabrication of Filter Banks for Implementation of Cavity Tunable Filter (캐비티 가변필터의 구현을 위한 필터뱅크 설계 및 제작)

  • Shin, Yeonho;Kang, Sanggee
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.14 no.6
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    • pp.169-173
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    • 2014
  • In order to satisfy user's requirements of needs for various services and to efficiently use of frequency, a communication system using one platform can support many communication services. Tunable filters must be used in the front end of broadband communication systems which provide and support various communication methods. In this paper we design and implement a filter bank to verify the feasibility of cavity tunable filter with the operation frequency of 800 MHz ~ 1600 MHz. The filter bank is composed of five bandpass filters and each bandpass filter has the same operation frequency band of the tunable filter. The implemented filter bank has the maximum insertion loss of 0.326 dB, the bandwidth of 37 MHz ~ 84 MHz, and the attenuation of minimum 19.974dB and mximum 37.812dB at the band edge ${\pm}60MHz$ over the operating frequency band.

A New Pulse Frequency Modulation(PFM) Series Boost Capacitor(SBC) Full Bridge DC/DC Converter (새로운 주파수 가변형(PFM) 직렬 부스트 캐패시터(SBC) 풀 브리지 DC/DC 컨버터)

  • Shin, Yong-Saeng;Jang, Young-Su;Roh, Chung-Wook;Hong, Sung-Soo;Lee, Hyo-Bum;Han, Sang-Kyoo
    • The Transactions of the Korean Institute of Power Electronics
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    • v.14 no.2
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    • pp.120-127
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    • 2009
  • This paper proposes a new Pulse Frequency Modulation(PFM)-Series Boost Capacitor(SBC) full bridge DC/DC Converter which features a high efficiency and high power density. The proposed converter controls the output voltage by varying the voltage across the series boost capacitor according to switching frequency and has no freewheeling period due to 50% fixed duty operation. As a result, its conduction loss is lower than that of the conventional phase shift full bridge converter. Moreover, ZVS of all power switches can be ensured along wide load ranges and output current ripple is very small. Therefore, it has very desirable merits such as a small output inductor, high efficiency, and improved heat generation. This paper performs a rationale and PSIM simulation of the proposed converter. Finally, experimental results from a 1.2kW(12V, 100A) prototype are presented to confirm the operation, validity and features of the proposed converter.