• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.34-40
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• 2011

This paper presents a low-dropout (LDO) linear regulator using ultra-low output impedance buffer for frequency compensation. The proposed buffer achieves ultra low output impedance with dual shunt feedback loops, which makes it possible to improve load and line regulations as well as frequency compensation for low voltage applications. A reference control scheme for programmable output voltage of the LDO linear regulator is presented. The designed LDO linear regulator works under the input voltage of 2.5~4.5V and provides up to 300mA load current for an output voltage range of 0.6~3.3V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5C
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• pp.520-529
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• 2007

In this paper, we study the characteristics of parameters which are related to performance of MCTF which is a key technique for wavelet-based scalable video coding, and propose an improved MCTF method. The proposed MCTF method adopts the motion estimation of which motion vector field is distributed more uniformly using variable block sizes. By using the proposed method, the decomposition performance of temporal filter is improved, and the energy in high-frequency frames is reduced. It can help the entropy coder to generate lower bitrate. From simulation results, we verify the decomposed energy on high-frequency frame using the proposed method is reduced by 25.86% at the most in terms of variance of the high-frequency frame.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.267-273
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• 2009

In this paper, we proposed a variable average operation for a WDR(Wide Dynamic Range). The previously proposed average operation [5] improves hardware efficiency and complexity by replacing divider with multiplier. However, the previously proposed method has some weak-points. For example, there are counting horizontal and vertical length, and then the multiplier selects a Mode set by the user when the lengths exactly correspond with the image's size in the Mode. To compensate some weak-points, we change a Mode selection methods as a using the image's total size. Also, we propose another feature that it can be applied to various image sizes. To get a more accurate average, we add an external compensation value. We design the variable average operation using a Verilog-HDL and confirm that the Serial Multiplier's structure is better efficiency than Split Multiplier's structure.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.41 no.6
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• pp.469-475
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• 2017

Workers in industrial fields are highly exposed to accidents or injuries caused by long working hours. An exoskeleton that is able to support the arm muscles of the worker and thereby reduce the probability of an accident and enhance working efficiency could be a solution to this problem. However, existing exoskeletons demand the use of high-priced sensors and motors, which makes them difficult to use in industrial fields. To solve this problem, we developed an arm assisting exoskeleton that consists only of mechanical components without any electronic sensors or motors. The exoskeleton follows the movement of the human arm by shoulder joint and ankle joint. In addition, counterbalance mechanisms are installed on the exoskeleton to support arm strength. The experimental validation of the exoskeleton was conducted using an EMG sensor, confirming the performance of the exoskeleton.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.4
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• pp.41-49
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• 2008

H.264/AVC supports variable block motion compensation, multiple reference images, 1/4-pixel motion vector accuracy, and in-loop deblocking filter, compared with the existing compression technologies. While these coding technologies are major functions of compression rate improvement, they lead to high complexity at the same time. For the H.264 video coding technology to be actually applied on low-end / low-bit rates terminals more extensively, it is essential to improve tile coding speed. Currently the deblocking filter that can improve the moving picture's subjective image quality to a certain degree is used on low-end terminals to a limited extent due to computational complexity. In this paper, a performance improvement method of the deblocking filter that efficiently reduces the blocking artifacts occurred during the compression of low-bit rates digital motion pictures is suggested. In the method proposed in this paper, the image's spatial correlational characteristics are extracted by using the variable block information of motion compensation; the filtering is divided into 4 modes according to the characteristics, and adaptive filtering is executed in the divided regions. The proposed deblocking method reduces the blocking artifacts, prevents excessive blurring effects, and improves the performance about $30{\sim}40%$ compared with the existing method.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.06a
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• pp.85-86
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• 2013

AT-DMB의 향상계층은 DQPSK 신호에 BPSK 또는 QPSK 신호를 더하여 변조하는 계층변조 방식을 사용하였기 때문에 수신기에서 채널 왜곡을 보상해야 신호의 복조가 가능하다. 다중 경로가 많은 지역에서는 주파수 선택적 페이딩이 발생하기 때문에 페이딩을 정확하게 추정하지 못하면 AT-DMB 향상계층 수신 성능이 저하되게 된다. 채널왜곡 추정을 위하여 AT-DMB 수신기에서는 채널추정 값을 스무딩하는 대역제한 필터를 사용한다. AT-DMB의 향상 계층 성능은 이 스무딩 필터의 대역폭에 따라 결정이 되며 적절한 필터 대역을 채널의 지연에 따라 설정해야 한다. 특히 SFN 환경에서는 수신 전력이 큰 둘 이상의 서로 다른 지연시간을 가지면서 수신이 되기 때문에 고정 대역폭 스무딩 필터를 사용한 채널왜곡 추정은 성능의 저하를 가져올 수 있다. 본 논문에서는 채널 지연 값을 추정하고 필터의 대역폭을 가변적으로 결정하는 방법에 대하여 설명하고 실험 결과를 보여준다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.6A
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• pp.782-793
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• 2000

This paper presents a simple dynamical prediction scheme of the signal level which is attenuated and varied due to rain fading in satellite communication links using above 10GHz frequency bands. The proposed prediction scheme has four functional blocks for discrete-time low-pass filtering, slope-based prediction, mean-error correction and hybrid fixed/variable prediction margin allocation. Through simulations using Ka-band attenuation data obtained from the data measured over Ku-band by frequency-scaling, it is shown that the slope-based prediction with the mean-error correction has as small standard deviation of prediction error as below 1 dB, and that the error is about 1.5 to 2.5 times as small as that without the mean-error correction. The hybrid prediction margin allocation requires smaller average margin than those of both fixed and variable methods.

• Journal of the Korean Society for Railway
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• v.17 no.3
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• pp.171-177
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• 2014

PWM converter trains exhibit excellent load characteristics in comparison with conventional phase-controlled trains with low power factors, as they can be operated at power factors which are close to unity by means of a voltage vector control method. However, in the case of a high track density or extended feeding, significant line losses and voltage drops can occur. Instead of operating these trains at a fixed unity power factor, this paper suggests a continuous optimal power factor control scheme for each train in an effort to minimize line losses and improve voltage drops according to varying load conditions. The proposed method utilizes the steepest descent algorithm targeting each car in the same feeding section to establish the optimized reactive power compensation levels that can minimize the reactive power loss of the feeder. The results from a simulation of a sample system show that voltage drops can be improved and line losses decreased.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.129-136
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• 2005

A multiplier generator, VPM_Gen (Variable-Precision Multiplier Generator), which generates Verilog-HDL models of multiplier cores with user-defined bit-width specification, is described. The bit-widths of operands are parameterized in the range of $8-bit{\sim}32-bit$ with 1-bit step, and the product from multiplier core can be truncated in the range of $8-bit{\sim}64-bit$ with 2-bit step, resulting that the VPM_Gen can generate 3,455 multiplier cores. In the case of truncating multiplier output, by eliminating the circuits corresponding to the truncation part, the gate counts and power dissipation can be reduced by about 40% and 30%, respectively, compared with full-precision multiplier. As a result, an area-efficient and low-power multiplier core can be obtained. To minimize truncation error, an adaptive error-compensation method considering the number of truncation bits is employed. The multiplier cores generated by VPM_Gen have been verified using Xilinx FFGA board and logic analyzer.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.4
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• pp.191-198
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• 2015

The purpose of this study is to develope a current variation control system appropriate to the various LED(Light Emitting Diode) lamps using current control system equipped with microcontroller based voltage regulator of power driving circuit. For this, we will suggest a stable control system of current variation to enable a stable power-supply and current-control, consisting of circuit to minimize the affects on the LED forward voltage using variable resistance and compensating resistance. The method of constant current circuit and energy savings using microcontroller based voltage regulator suggested in this study can be applied to various a big capacity LED lamp to minimize the unnecessay heat generation and to control resistace delicately. Ultimately, we expect the results of this study will upgrade the reliability of LED lamp by supplying the current stably.