• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.87-95
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• 2009

In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate4eve1 circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.80-88
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• 2007

High adaptability and scalability are two critical issues in implementing a very complex system in a single chip. To obtain high adaptability and scalability, novel system design methodology known as communication-based system design has gained large attention from SoC designers. NoC (Network-on-Chip) is such an on-chip communication-based design approach for the next generation SoC design. To provide high adaptability and scalability, NoCs employ network interfaces and routers as their main communication structures and transmit and receive packetized data over such structures. However, data packetization, and routing overhead in terms of run time and area may cost too much compared with conventional SoC communication structure. Therefore, in this research, we propose a novel methodology which automatically generates a hybrid communication structure. In this work, we map traditional pin-to-pin wiring structure for frequent and timing critical communication, and map flexible and scalable structure for infrequent, or highly variable communication patterns. Even though, we simplify the communication structure significantly through our algorithm the connectivity or the scalability of the communication modules are almost maintained as the original NoC design. Using this method, we could improve the timing performance by 49.19%, and the area taken by the communication structure has been reduced by 24.03%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.2A
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• pp.139-147
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• 2008

DVB-S2 (Digital Video Broadcasting-Satellite, Version 2) system transmits frames which adapt their structures based on the channel conditions, thus requiring simultaneous detection of the start of the Same (SoF) and the frame structure at the initial acquisition stage of the receiver. Also, a very low value of the minimum operating signal-to-noise ratio (SNR) for the acquisition necessitates a method utilizing multiple received frames to meet the required performance. In this paper, performance of joint time synchronization and frame structure detection methods using multiple DVB-S2 frames is evaluated by deriving the detection error probability. In particular, we evaluate the performance and complexity variations when the soft- and hard-decision values of the signal correlation output are used, present the synchronization parameters to optimize the performance, and verify the analysis results via computer simulations.

• Journal of Advanced Navigation Technology
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• v.24 no.2
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• pp.85-91
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• 2020

Recently, a multi-mode radar system was designed for efficient operation of unmanned aerial vehicles (UAVs) in various environments, which has the advantage of being able to integrate and utilize methods of the pulse Doppler (PD) radar and the frequency modulated continuous wave (FMCW) radar. For the range detection part of the multi-mode radar signal processor (RSP), the hardware structure using the FFT processor and the IFFT processor is required to be designed in a way that improves efficiency on the area side. In addition, given the radar application environment that requires a variety of distance resolutions, FFT processors need to support variable-length operations. In this paper, the FFT processor and IFFT processor in multi-mode RSP range estimation are designed and proposed as hardware for a single FFT processor that supports variable length operation of 16-1024 points. The proposed FFT processor designed in hardware description language (HDL) and can be implemented with 7,452 logic elements and 5,116 registers.

• The Journal of the Acoustical Society of Korea
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• v.41 no.5
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• pp.507-517
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• 2022

The PhotoAcoustic Microscopy (PAM) has been proved to be a useful tool for biological and medical applications due to its high spatial and contrast resolution. PAM is based on transmission of laser pulses and reception of PA signals. Since the strength of PA signals is generally low, not only are high-performance optical and acoustic modules required, but high-performance electronics for imaging are also particularly needed for high-quality PAM imaging. Most PAM systems are implemented with a combination of several pieces of equipment commercially available to receive, amplify, enhance, and digitize PA signals. To this end, PAM systems are inevitably bulky and not optimal because general purpose equipment is used. This paper reports a PA signal receiving system recently developed to attain the capability of improved Signal to Noise Ratio (SNR) and Contrast to Noise Ratio (CNR) of PAM images; the main module of this system is a low noise, wideband signal receiver that consists of two low-noise amplifiers, two variable gain amplifiers, analog filters, an Analog to Digital Converter (ADC), and control logic. From phantom imaging experiments, it was found that the developed system can improve SNR by 6.7 dB and CNR by 3 dB, compared to a combination of several pieces of commercially available equipment.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.20 no.6
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• pp.761-767
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• 2007

In centralized control system, complicated control systems including sensors, power supply and dampers should be required to satisfy the target response of large-scale structures. The practical applications of the centralized control system, however, is very difficult due to high order finite element model of structures, uncertainty of models, and limitations of the excitation system. In this study, the decentralized response-dependent MR damper of which magnetic field is automatically modulated according to the displacement or velocity transferred to the damper without any sensing and computing systems. this decentralized response-dependent MR damper are investigated according to the ranges of relative magnitude between the control force of MR damper and the story shear force of structures by nonlinear time history analysis. Finally, its performance is compared with centralized LQR algorithm which is used in general centralized control theory for a three story building structure.

• Journal of Institute of Control, Robotics and Systems
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• v.2 no.4
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• pp.279-286
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• 1996

In this paper, variable structure control(VSC) based on reaching law method with fuzzy inference for nonlinear systems is proposed. The reaching law means the reaching condition which forces an initial state of system to reach switching surface in finite time, and specifies the dynamics of a desired switching function. Since the conventional reaching law has fixed coefficients, the chattering can be existed largely in sliding mode. In the design of a proposed fuzzy reaching law, we fuzzify RP(representative point)'s orthogonal distance to switching surface and RP's distance the origin of the 2-dimensional space whose coordinates are the error and the error rate. The coefficients of the reaching law are varied appropriately by the fuzzy inference. Hence the state of system in reaching mode reaches fastly switching surface by the large values of reaching coefficients and the chattering is reduced in sliding mode by the small values of those. And the effectiveness of the proposed fuzzy reaching law method is showen by the simulation results of the control of a two link robot manipulator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.8
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• pp.1685-1691
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• 2004

The objective of this study is aimed at reducing the contour error of AC Servo derives by improving the interpolation error of each axis through variable structure control system. The errors in machining process by AC Servo motor are due to many elements, such as the delay of the servo drivers, friction and the gain mismatch between x axis and y axis motors and so on. Sliding mode control system is applied to a AC servo drive as a numerical example in this paper. The experiment results which are compared with those of typical PI scheme show the validity of improvement in circular interpolation error of the system.

• Journal of the Korean Society for Precision Engineering
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• v.14 no.3
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• pp.98-106
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• 1997

In this paper, a new method of position synchronizing control is proposed for multi-axes driving system. The proposed position synchronizing control system is constituted with speed and synchronizing controller. The speed controller is aimed at the following to speed reference. Furthermore, it is designed to guarantee low sensitivity under some disturbance as well as robustness against model uncertainties using $H_{\infty}$technique. The synchronizing controller is designed to keep minimizing the position error using PID control law which is considered to reduce the dimension of transfer function in the control system. Especially, the proposed method can be easily conducted by controlling only slave axis speed, because it, has variable structure which is decided to master and slave axis by the sign of synchronizing error. Therfore, the master axis which is smaller influenced than another axes by disturbance can be controlled without reducing or increasing its speed for precise position synchronization. The effectiveness of the proposed method is sucessfully confirmed through many experiments.s.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.313-316
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• 2005

본 논문은 대용량 진력변환장치인 멀티-레벨 인버터 시스템에서 출력 전압가변이 손쉬운 HBML(H-Bridge Multi-Level) 인버터의 Master와 Cell 제어기 구성에 관한 것이다. HBML 인버터는 각각의 단위 Cell을 저압에서 사용하는 인버터로 구성하면, 구조적으로 풀-브릿지(Full-Bridge) 인버터를 캐스케이드 방식으로 연결하여 고압출력을 얻을 수 있는 토폴로지이다. 시스템에서 Master와 Cell의 제어 처리를 한곳에 집중하지 않는 분산 제어 방식을 적용하여 통신 Data를 최적화하도록 구성하고, 이를 바탕으로 두 제어기를 고성능 원-칩(One-Chip) DSP로만 설계하였다. 모든 외부 모듈을 내장한 CPU로 제어기가 구성될 경우, 외부 노이즈에 강하며, 추가되는 하드웨어 결선을 최소화할 수 있다. 본 논문에서는 HBML 인버터 출력 생성 시 반드시 요구되는 출력 PWM 동기 및 위상전이(Phase Shift)를 각 제어기 자체에 내장된 모듈만을 이용해서 구현하였다.