• The Korean Journal of Food And Nutrition
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• v.28 no.3
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• pp.396-403
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• 2015

To improve the shelf-life of cherry tomato, samples were treated with aqueous chlorine dioxide ($ClO_2$) at 30 ppm for 0~30 minutes and the weight loss rate as well as the changes in physico-chemical and sensory properties of treated samples were investigated. Weight change in the control and in the samples with aqueous $ClO_2$ treatment were decreased slightly, and there were no difference during the storage period. There were no differences in soluble solid content among the treatments and during the storage period. There were no differences in the firmness of samples among the treatments but the firmness of the aqueous $ClO_2$ treated samples were decreased slower than that of the control samples. No significant changes in lightness, redness and yellowness of the controls and the samples by aqueous $ClO_2$ treatment were observed during 4 weeks storage period. The sensory parameters including taste, flavor, color, texture and overall acceptance at the initial period did not differ among the treatments. The scores for taste, texture and overall acceptance of the control were decreased faster than those of the aqueous $ClO_2$ treated samples when 3 weeks reached.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.72-81
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• 2011

In this paper, we proposed and designed a novel floating point converter which supports single and double precisions of IEEE754 standard. The proposed convertor supports conversions between floating point number single/double precision and signed fixed point number(32bits/64bits) as well as conversions between signed integer(32bits/64bits) and floating point number single/double precision and conversions between floating point number single and double precisions. We defined a new internal format to convert various input types into one type so that overflow checking could be conducted easily according to range of output types. The internal format is similar to the extended format of floating point double precision defined in IEEE754 2008 standard. This standard specifies that minimum exponent bit-width of the extended format of floating point double precision is 15bits, but 11bits are enough to implement the proposed converting unit. Also, we optimized rounding stage of the convertor unit so that we could make it possible to operate rounding and represent correct negative numbers using an incrementer instead an adder. We designed single cycle data path and 5 cycles data path. After describing the HDL model for two data paths of the convertor, we synthesized them with TSMC 180nm technology library using Synopsys design compiler. Cell area of synthesis result occupies 12,886 gates(2 input NAND gate), and maximum operating frequency is 411MHz.

• Journal of the Korean Geographical Society
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• v.31 no.4
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• pp.672-684
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• 1996

This paper explores the inter-ethnic conflicts between Blocks and Hispanics focusing on the emergent Hispanic ethnictity that reveals situational character in the US contexts. In the US census categories, major groups are indetified by race and ethnicity in which the Hispanic orgin is a category based on their common language while diverse in nationality. The census defined Hispanic category extends conveniently to acquiesce Affirmative Action and other government resource distribution. Internally, Hispanics have established numerous organizations to coalesce and assure their interests. The achieved dual language program and jurisdictional revision to represent language minority work as leverages to their cohesiveness. Under diminishing public resources and welfare payment, it is more difficult sharing burdens than benefits between minority groups. Block are not comfortable with the benefits Hispanics receive form the civil rights achievement without having had to struggle for it. The ethnic conflicts of the have-nots have become a new ethnic phenomenon attributable to the emergent Hispanic ethnicity.

• Journal of the Society of Cosmetic Scientists of Korea
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• v.46 no.1
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• pp.57-65
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• 2020

To prevent loss of hair protein during hair washing process by water through, a shield coating the pathway of water molecules was studied. Hydrophobic virgin hair, hydrophilic hair, which was damaged only methyleicosanoic acid (18-MEA) on the surface, and a repaired hair re-bound 18-MEA, were prepared and water mass changes by as heat were measured. Results showed that hydrophobic hairs followed bi-exponential function of 39 s and 151 s and other two hairs exhibited fast- and mono-exponential decay with 83 s, reflecting the extraction of water molecules without any resistance at the hydrophobic surface. On the assumption that hydrophobic surface resists an extraction of protein in water during the wash, the protein concentrations were compared from the hair of hydrophobic and hydrophilic surface. The extracted hair proteins were 179 and 148 ㎍/mL from the hair coated with hydrophilic polyethylene glycol (PEG) and hydrophobic polydimethylsiloxane (PDMS), respectively. This study suggested that hydrophobic coating on the hair surface could be used to prevent protein loss in wash, represented by LFM. In conclusion, this research provides some useful information to contribute to the development of hair washing products that can prevent protein loss in the cleaning process by granting hydrophobic coatings.

• Korean Chemical Engineering Research
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• v.62 no.1
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• pp.105-111
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• 2024

The SLA (Stereolithography Apparatus) method is a type of 3D printing technique predicated on the transformation of liquid photocurable resin into a solid form through UV laser exposure, and its application is increasing in various fields. In this study, we conducted research to enhance the hydrophobicity and transparency of SLA 3D printing surfaces for microfluidic system production. The enhancement of surface hydrophobicity in SLA outputs was attainable through the application of hydrophobic coating methods, but the coating durability under different conditions varied depending on the type of hydrophobic coating. Additionally, to simultaneously achieve the required transparency and hydrophobic properties for the fabrication of microfluidic systems, we applied hydrophobic coatings to the proposed transparency enhancement method from prior research and compared the changes in contact angles. Teflon coating was proposed as a suitable hydrophobic coating method for the fabrication of microfluidic systems, given its excellent transparency and high coating durability in various environmental conditions, in comparison to titanium dioxide coating. Finally, we produced an Electrophoresis of Charged Droplet (ECD) chip, one of the digital microfluidics systems, using SLA 3D printing with the proposed Teflon coating method (Fluoropel 800). Droplet manipulation was successfully demonstrated with the fabricated chip, confirming the potential application of SLA 3D printing technology in the production of microfluidic systems.

• The KIPS Transactions:PartA
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• v.13A no.3 s.100
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• pp.185-190
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• 2006

JPEG 2000 is used as an alternative to solve the blocking artifact problem with the existing still image compression JPEG algorithm. However, it has shortcomings such as longer floating point computation time and more complexity in the procedure of enhancing the image compression rate and decompression rate. To compensate for these we implemented with hardware the JPEG 2000 algorithm's filter part which requires a lot of floating point computation. This DWT Filter[1] chip is designed on the basis of Daubechies 9/7 filter[6] and is composed of 3-stage pipeline system to optimize the performance and chip size. Our implemented Filter was 7 times faster than software based Filter in the floating point computation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.886-889
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• 2006

수치연산 보조프로세서로도 알려져 있는 부동 소수점 연산장치(FPU)는 컴퓨터가 사용하는 기본 마이크로프로세서보다 더 빠르게 숫자를 다를 수 있는 특별한 회로 설계 또는 마이크로프로세서를 말한다. FPU는 전적으로 대형 수학적 연산에만 초점을 맞춘 특별한 명령 셋을 가지고 있어서 그렇게 빠르게 계산을 수행할 수 있는 것이다. FPU는 오늘날의 거의 모든 PC에 장착되고 있지만, 실은 그것은 그래픽 이미지 처리나 표현 등과 같은 특별할 일을 수행할 때에 필요하다. 초창기 컴퓨터 회사들은 각기 다른 연산방식을 사용했다. 이에 따라 연산결과가 컴퓨터마다 다른 문제점을 해결하기 위해 IEEE에서는 부동 소수점에 대한 표준안을 제안하였다. 이 표준안은 IEEE Standard 754 이며, 오늘날 인텔 CPU 기반의 PC, 매킨토시 및 대부분의 유닉스 플랫폼에서 컴퓨터 상의 실수를 표현하기 위해 사용하는 가장 일반적인 표현 방식으로 발전하였다. 본 논문에서는 부동 소수점 표준안 중 32-bit 단일 정밀도 부동 소수점 가산기를 VHDL로 구현하여 FPGA칩으로 다운하고 PCI 인터페이스를 통해 Visual C++로 데이터의 입출력을 검증하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.809-811
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• 2010

In most floating-point operations related with 3D graphic applications for mobile devices, properly approximated data calculations with reduced complexity and low power are preferable to exactly rounded floating-point operations with unnecessary preciseness with cost. Among all the sophisticated floating-point arithmetic operations, multiplication and division are the most complicated and time-consuming, and they can be transformed into addition and subtraction repectively by adopting the logarithmic conversion. In this process, the most important factor for performance is how high we can make an approximation of the logarithm conversion. In this paper, we cover the trends in studying the logarithm conversion circuit designs. We also discuss the important factor in design issues and the applicable fields in detail.

• Journal of Korean Society of Rural Planning
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• v.23 no.4
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• pp.1-13
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• 2017

베트남 북부 산악지형에 거주하는 소수 부족민들의 생계개선이 베트남 정부의 정책적인 지원 사업에도 불구하고 현재까지 뚜렷한 성과를 내지 못하는 것으로 알려져 왔다. 특히 지속가능한 개발 및 인적자원개발을 목표로 하고 있는 베트남 경제사회개발정책(2011~2020)의 하위전략인 신농촌 개발정책(New Rural Development)에 의한 사업들이 적절히 수행되고 있는지 의문이 대두되었다. 한편, 베트남 라오까이성 행복프로그램은 한국 코이카 재원으로 새마을운동 경험과 정신을 바탕으로 설계되었으며 심각한 빈곤상태에 있는 성내 8개 소수부족민 마을에 마을특성과 주민 의견이 반영된 개발계획을 수립하고 계획실행의 주체인 마을주민들과 현장 공무원에게 다양한 훈련 사업들을 제공하였다. 본 연구는 생계개선에 대한 이론 고찰과 함께 한국 및 베트남의 농촌개발 경험사례 분석을 바탕으로 프로그램의 다양한 역량강화 사업들이 8개 소수부족 주민들의 의식변화와 생계자산 향상에 어떠한 영향을 끼쳤는지 알아보았다. 본 연구결과는 프로그램에서 제공한 다양한 역량강화 훈련들이 주민의식의 긍정적인 변화와 소수 부족민들의 생계자산에 대하여 상당한 만족도를 가져왔는바, 신농촌 개발정책은 직접자재 위주의 지원을 줄이는 대신 주민들의 자신감 고취를 위한 주민의식 교육과 주민들의 생계활동 능력향상을 위한 다양한 훈련 사업을 확대해야 함을 보여준다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.547-554
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• 2008

In this paper, two-stage pipelined floating-point multiplier (FP-MUL) is designed. The FP-MUL processor supports single precision multiplication for 3D graphic APIs, such as OpenGL and Direct3D and has area-efficient and low-latency architecture via saturated arithmetic, area-efficient sticky-bit generator, and flagged prefix adder. The FP-MUL has about 4-ns delay time under $0.13{\mu}m$ CMOS standard cell library and consists of about 7,500 gates. Because its maximum performance is about 250 MFLOPS, it can be applicable to mobile 3D graphics application.