• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.11
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• pp.934-940
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• 2001

Magnetic properties were investigated for Si/SiO$_2$/NiFe(300 )/A1$_2$O$_3$(t)/Co(200 ) junction related with the parameters of $Al_2$O$_3$. Insulating $Al_2$O$_3$ layer was formed by depositing a 5~40 thick Al layer, followed by a 90~120s RF plasma oxidation in an $O_2$ atmosphere. Magnetoresistance was not observed for tunnel junction with 5~10 thick Al layer, but magnetoresistance was observed large for tunnel junction with 15~40 thick Al layer. Oxidation time did not largely influence magnetoresistance. Tunnel magnetoresistance effect depended on magnetization behavior of two ferromagnetic layers. Tunneling junction was confirmed through nonlinear I-V curve. In this work, tunneling magnetoresistance(TMR) up to 30 % was observed. This apparent TMR is an artifact of the nonuniform current flow over the junction in the cross geometry of the electrodes.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.865-870
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• 2003

The MFIS (Metal-Ferroelectric-Insulator-Semiconductor) capacitors were fabricated using a metalorganic decomposition method. Thin layers of CeO$_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the CeO$_2$ layer. The morphology of films and the interface structures of the BLT and the CeO$_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 2.82 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• Journal of the Korean Ceramic Society
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• v.52 no.1
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• pp.72-76
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• 2015

150-nm-thick In-Zn-Tin-Oxide (IZTO) films were deposited by RF magnetron sputtering after a 10 to 50-nm-thick $SiO_2$ buffer layer was deposited by plasma enhanced chemical vapor deposition (PECVD) on polyethylene terephthalate (PET) substrates. The electrical, structural, and optical properties of the IZTO/$SiO_2$/PET films were analyzed with respect to the thickness of the $SiO_2$ buffer layer. The mechanical properties were outstanding at a $SiO_2$ thickness of 50 nm, with a resistivity of $1.45{\times}10^{-3}{\Omega}-cm$, carrier concentration of $8.84{\times}10^{20}/cm^3$, hall mobility of $4.88cm^2/Vs$, and average IZTO surface roughness of 12.64 nm. Also, the transmittances were higher than 80%, and the structure of the IZTO films were amorphous, regardless of the $SiO_2$ thickness. These results indicate that these films are suitable for use as a transparent conductive oxide for transparency display devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.439-444
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• 2005

We investigated the structural and electrical properties of BLT films grown on Si covered with $ZrO_{2}$ buffer layer. The BLT thin film and $ZrO_{2}$ buffer layer were fabricated using a metalorganic decomposition method. The electrical properties of the MFIS structure were investigated by varying thickness of the $ZrO_{2}$ layer. AES and TEM show no interdiffusion and reaction that suppressed using the $ZrO_{2}$ film as a buffer layer The width of the memory window in the C-V curves for the MFIS structure decreased with increasing thickness of the $ZrO_{2}$ layer. It is considered that the memory window width of MFIS is not affected by remanent polarization. Leakage current density decreased by about four orders of magnitude after using $ZrO_{2}$ buffer layer. The results show that the $ZrO_{2}$ buffer layers are prospective candidates for applications in MFIS-FET memory devices.

• Journal of the Korean Vacuum Society
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• v.16 no.3
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• pp.215-220
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• 2007

Thin films of $SBT(SrBi_2Ta_2O_9)$ having $Pt/SBT/Seed/Pt/Ti/SiO_2/Si$ structure were fabricated using self-seed layer method by R.F. Magnetron sputter. Self-seed layers were deposited at room temperature and $600^{\circ}C$, which had 30 nm thickness. To investigate crystallization of self-seed layer we characterized by XRD after various heat treatment. And we characterized the crystallinity and electrical properties of SBT on self-seed layer after various heat treatment.

• Journal of the Korean institute of surface engineering
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• v.41 no.4
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• pp.169-173
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• 2008

The objective of this study is to coat the $SiO_2$ layer uniformly on the ZnS:Cu phosphors by using Sol-Gel method. From results of SEM micrographs observation, XRD and XPS analysis, it could be confirmed that $SiO_2$ layer was relatively well coated on ZnS:Cu particles. $Ag_2S$ was used as a decoding chemical to analyze the dense and uniform coating performance of $SiO_2$ layer on phosphor particles. It could be concluded that phosphors synthesized from our two step replacement method showed strong blue peak comparing to other method and rather weak green peak also. Obtained particle size of phosphors were about 20m diameter. Luminescence properties of the phosphors were examined by photoluminescence spectra at the excitation wavelength of 270 nm.

• Journal of the Korean Vacuum Society
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• v.20 no.1
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• pp.50-56
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• 2011

In this study, the effects of ZnO buffer layer thickness and annealing temperature on the heterojunction diode, ZnO/b-ZnO/p-Si(111), were reported. The effects of those on the structural and electrical properties of zinc oxide (ZnO) films on ZnO buffered p-Si (111) substrate were also studied. Structural properties of ZnO thin films were studied by X-ray diffraction and I-V characteristics were measured by a semiconductor parameter analyzer. ZnO thin films with 70 nm thick buffer layer and annealing temperature of $700^{\circ}C$ showed the best c-axis preferred orientation. The best electrical property was found at the condition of buffer layer annealing temperature of $700^{\circ}C$ and 50nm thick ZnO buffer layer (resistivity: $2.58{\times}10^{-4}[{\Omega}-cm]$, carrier concentration: $1.16{\times}1020[cm^{-3}]$). The I-V characteristics for ZnO/b-ZnO/p-Si(111) heterojunction diode were improved with increasing buffer layer thickness at buffer layer annealing temperature of $700^{\circ}C$.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.2
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• pp.242-248
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• 1996

The properties of TiN/TiSi$_{2}$ bilayer formed by a rapid thermal annealing is investigated when thin SiO$_{2}$ film exists at the Ti-Si interface. The competitive reaction for the TiN/TiSi_2 bilayer occurs above 600 .deg. C. The thickness of the TiSi$_{2}$ layer decreases with increasing SiO$_{2}$ film thickness and also decreases with increasing anneal temperture When the competitive reaction for the TiN/TiSi$_{2}$ bilayer is occured by rapid thermal annealing, the composition of TiN layer represents TiN$_{x}$O$_{y}$ due to the SiO$_{2}$ layer at the Ti-Si interface but the structures of the TiN and TiSi$_{2}$ layers were not changed.d.d.

• The Korean Journal of Ceramics
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• v.1 no.3
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• pp.160-164
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• 1995

Mechanical and chemical tests were performed on $Zro_2 \cdot SiO_2$ glass fibers manufactured by the sol-gel method and E-glass fibers-reinforced cement composites in order to investigate the interactions between glass fibers and cement matrices. Chemical attack leads to corrosion of the glass fiber surfaces. In the corrosion reactions, the surface of $30ZrO_2 \cdot 70 SiO_2$ glass fibers developed a densified concentric layer, which consists of glass corrosion products with much higher Zr and lower Si than the fresh glass fiber. The layer of reaction product is regarded to stiffen the cement matrices and provide a useful improvement to the mechanical properties. The addition of $ZrO_2$ content increases the corrosion resistance of glass fibers in cement by forming a passivating layer on the surface of glass fibers.