• Transactions on Electrical and Electronic Materials
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• 제5권5호
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• pp.169-172
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• 2004

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a $N_2$O gate oxide 30 $\AA$ by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for $N_2$O gate oxide 30 $\AA$, ultra thin gate oxide 30 $\AA$ was formed by using the $N_2$O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi$_2$ process was performed by RTP annealing at 850 $^{\circ}C$ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ～ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 $\AA$ proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 $\AA$ $N_2$O gate oxide.

• 한국정보통신학회논문지
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• 제3권2호
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• pp.471-475
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• 1999

$N{_2}O$ 게이트 산화막을 사용한 nMOSFET가 금속 플라즈마 식각 피해에 대한 면역도가 동일한 두께의 순수한 산화막을 갖는 nMOSFET보다 향상됨을 보여준다. Area Antenna Ratio(AAR)를 증가시킴에 따라 $N{_2}O$ 산화막을 갖는 nMOSFET는 좁은 초기 분포 특성과 정전계 스트레스하에서 더 작은 열화특성을 보이는 데 이는 Si기판과 산화막 계면에서의 질소기의 영향으로 설명되어진다. 또한 $N{_2}O$ 게이트 산화막을 사용하면 순수한 게이트 산화막을 사용할 때 보다 금속 Area Antenna Ratio(AAR)과 Perimeter Area ratio(PAR) 의 최대 허용 크기를 더 증가할 수 있다. 이러한 $N{_2}O$ 게이트 산화막을 갖는 NMOSFET의 개선은 Si기판과 $N{_2}O$ 산화막 계면에 있는 질소기에 의한 계면 강도의 영향 때문으로 판단된다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.176-176
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• 2003

The effects of oxide thickness and gate length of MgO/GaN metal oxide semiconductor field effect transistors (MOSFETs) on I-V, threshold voltage and breakdown voltage characteristics were examined using a drift-diffusion model. The saturation drain current scales in an inverse logarithmic fashion with MgO thickness and is < 10$^{-3}$ A.${\mu}{\textrm}{m}$$^{-1}$ for 0.5 ${\mu}{\textrm}{m}$ gate length devices with oxide thickness > 600 $\AA$ or for all 1 ${\mu}{\textrm}{m}$ gate length MOSFETs with oxide thickness in the range of >200 $\AA$. Gate breakdown voltage is > 100 V for gate length >0.5 ${\mu}{\textrm}{m}$ and MgO thickness > 600 $\AA$. The threshold voltage scales linearly with oxide thickness and is < 2 V for oxide thickness < 800 $\AA$ and gate lengths < 0.6 ${\mu}{\textrm}{m}$. The GaN MOSFET shows excellent potential for elevated temperature, high speed applications.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.17-19
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• 2004

The electrical properties of gate oxides grown in two different processes, which are in 10% nitrous oxide($N_2O$) and in dry oxygen, have been experimentally investigated and compared. It has been observed that the $SiC-SiO_2$ interface-trap density(Dit) measured in nitrided gate oxide has been tremendously reduced, compared to the density obtained from gate oxide grown in dry oxygen. The beneficial effects of nitridation on gate oxides also have been demonstrated in the values of total near interface-trap density and of forward-bias breakdown field. The reasons of these improvements have been explained.

• 전자공학회논문지D
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• 제35D권12호
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• pp.68-74
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• 1998

본 논문에서는 electron cyclotron resonance (ECR) N₂O-플라즈마 산화막을 게이트 산화막으로 사용한 다결정 실리콘 박막 트랜지스터 (TFT)의 성능과 단채널 특성에 대하여 연구하였다. ECR NE₂O-플라즈마 게이트 산화막을 사용한 소자는 열산화막을 이용한 경우에 비해 우수한 성능과 억제된 단채널 효과를 나타낸다. 얇은 ECR N2O-플라즈마 산화막을 사용하여 n채널 TFT의 경우 3 ㎛, p채널 TFT의 경우 1㎛ 게이트 길이까지 문턱 전압 감소가 없는 소자를 얻었다. 이러한 특성 향상은 부드러운 계면, passivation 효과, 그리고 계면과 박막 내부에 존재하는 강한 Si ≡ N 결합 등에 기인한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 추계학술대회 논문집
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• pp.90-93
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• 1992

In this paper, MOS characteristics of gate dielectrics prepared by furnace oxidation of Si in an $N_2O$ ambient have been studied. Compared with the oxides grown in $O_2$, $N_2O$ oxides show significantly improved breakdown field and low flat band voltage. Also, $N_2O$ oxide is more controllable for ultrathin film growth than $O_2$ oxide. This improvement is caused by nitrogen incorporation into the $N_2O$ oxide. Therefore, the nitrogen-rich-layer at the Si/$SiO_2$ interface formed during $N_2O$ oxidation not only strengthen $N_2O$ oxide structure at the interface and improves the gate dielectric quality, it also acts as a oxidant diffusion barrier that reduces the oxidation rate significantly.

• 한국전기전자재료학회논문지
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• 제26권3호
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• pp.177-182
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• 2013

Transparent thin film transistors (TTFT) were fabricated on $N^+$ Si wafers. $SiO_2$, $Si_3N_4/SiO_2$ and $Al_2O_3/SiO_2$ grown on the wafers were used as gate insulators. The rf magnetron sputtered zinc tin oxide (ZTO) films were adopted as active layers. $N^+$ Si wafers were wet-oxidized to grow $SiO_2$. $Si_3N_4$ and $Al_2O_3$ films were deposited on the $SiO_2$ by plasma enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD), respectively. The mobility, $I_{on}/I_{off}$ and subthreshold swing (SS) were obtained from the transfer characteristics of TTFTs. The properties of gate insulators were analyzed by comparing the characteristics of TTFTs. The property variation of the ZTO TTFTs with time were observed.

• 한국진공학회지
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• 제10권3호
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• pp.328-334
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• 2001

초박막 게이트 유전막 및 비휘발성 기억소자의 게이트 유전막으로 연구되고 있는 NO/$N_2$O 질화산화막 및 재산화질화산화막의 특성을 D-SIMS(dynamic secondary ion mass spectrometry), ToF-SIMS(time-of-flight secondary ion mass spectrometry), XPS(x-ray Photoelectron spectroscopy)으로 조사하였다. 시료는 초기산화막 공정후에 NO 및 $N_2$O 열처리를 수행하였으며, 다시 재산화공정을 통하여 질화산화막내 질소의 재분포를 형성토록 하였다. D-SIMS 분석결과 질소의 중심은 초기산화막 계면에 존재하며 열처리 공정에서 NO에 비해서 $N_2$O의 경우 질소의 분포는 넓게 나타났다. 질화산화막내 존재하는 질소의 상태를 조사하기 위하여 ToF-SIMS 및 XPS 분석을 수행한 결과 SiON, $Si_2$NO의 결합이 주도적이며 D-SIMS에서 조사된 질소의 중심은 SiON 결합에 기인한 것으로 예상된다. 재산화막/실리콘 계면근처에 존재하는 질소는 $Si_2$NO 결합형태로 나타나며 이는 ToF-SIMS로 얻은 SiN 및 $Si_2$NO 결합종의 분포와 일치하였다.

• 한국정보전자통신기술학회논문지
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• 제16권4호
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• pp.180-186
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• 2023

본 논문은 4세대 VNAND 공정으로 만들어진 고전압 SiO2 절연층 nMOSFET의 n⁺ 및 p⁺ poly-Si 게이트에서의 positive bias temperature instability(PBTI) 열화에 대해 비교하고 각각의 메커니즘에 대해 분석한다. 게이트 전극 물질의 차이로 인한 절연층의 전계 차이 때문에 n⁺/nMOSFET의 열화가 p⁺/nMOSFET의 열화보다 더 클 것이라는 예상과 다르게 오히려 p⁺/nMOSFET의 열화가 더 크게 측정되었다. 원인을 분석하기 위해 각각의 경우에 대해 interface state와 oxide charge를 각각 추출하였고, 캐리어 분리 기법으로 전하의 주입과 포획 메커니즘을 분석하였다. 그 결과, p⁺ poly-Si 게이트에 의한 정공 주입 및 포획이 p⁺/nMOSFET의 열화를 가속시킴을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권2호
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• pp.95-102
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• 2001

Hafnium oxide thin films for gate dielectric were deposited at $300^{\circ}C$ on p-type Si (100) substrates by plasma enhanced chemical vapor deposition (PECVD) and annealed in $O_2$ and $N_2$ ambient at various temperatures. The effect of hydrogen treatment in 4% $H_2$ at $350^{\circ}C$ for 30 min on the electrical properties of $HfO_2$for gate dielectric was investigated. The flat-band voltage shifts of $HfO_2$capacitors annealed in $O_2$ambient are larger than those in $N_2$ambient because samples annealed in high oxygen partial pressure produces the effective negative charges in films. The oxygen loss in $HfO_2$films was expected in forming gas annealed samples and decreased the excessive oxygen contents in films as-deposited and annealed in $O_2$ or $N_2$ambient. The CET of films after hydrogen forming gas anneal almost did not vary compared with that before hydrogen gas anneal. Hysteresis of $HfO_2$films abruptly decreased by hydrogen forming gas anneal because hysteresis in C-V characteristics depends on the bulk effect rather than $HfO_2$/Si interface. The lower trap densities of films annealed in $O_2$ambient than those in $N_2$were due to the composition of interfacial layer becoming closer to $SiO_2$with increasing oxygen partial pressure. Hydrogen forming gas anneal at $350^{\circ}C$ for samples annealed at various temperatures in $O_2$and $N_2$ambient plays critical role in decreasing interface trap densities at the Si/$SiO_2$ interface. However, effect of forming gas anneal was almost disappeared for samples annealed at high temperature (about $800^{\circ}C$) in $O_2$ or $N_2$ambient.