• Transactions on Electrical and Electronic Materials
• /
• 제4권3호
• /
• pp.34-37
• /
• 2003

[ $HfO_2$ ] and $HfO_xN_y$ films were deposited by plasma-enhanced chemical vapor deposition using $Hf[OC(CH_3)_3]_4$ as the precursor in the absence of $O_2$. The crystallization temperature of the $HfO_xN_y$ films is higher than that of the $HfO_2$ film. Nitrogen incorporation in $HfO_xN_y$ was confirmed by auger electron spectroscopy analysis. After post deposition annealing (PDA) at 800$\Box$, the EOT increased from 1.34 to 1.6 nm in the $HfO_2$ thin films, whereas the increase of EOT was suppressed to less than 0.02 nm in the $HfO_xN_y$. The leakage current density decreased from 0.18 to 0.012 $A/cm^2$ with increasing PDA temperature in the $HfO_2$ films. But the leakage current density of $HfO_xN_y$ does not vary with increasing PDA temperature because an amorphous $HfO_xN_y$ films suppresses the diffusion of oxygen through the gate dielectric.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 하계학술대회 논문집
• /
• pp.45-49
• /
• 2001

We have investigated physical and electrical properties of the Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin film for alternative gate dielectrics in the metal-oxide-semiconductor device. The oxidation of Hf deposited directly on the Si substrate results in the H $f_{x}$/ $O_{y}$ interfacial layer and the high-k Hf $O_2$film simultaneously. Interestingly, the post-oxidation N2 annealing of the H102/H1Si70y thin films reduces(increases) the thickness of an amorphous HfS $i_{x}$/ $O_{y}$ layer(Hf $O_2$ layer). This phenomenon causes the increase of the effective dielectric constant, while maintaining the excellent interfacial properties. The hysteresis window in C-V curves and the midgap interface state density( $D_{itm}$) of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin films less than 10 mV and ~3$\times$10$^{11}$ c $m^{-2}$ -eV without post-metallization annealing, respectively. The leakage current was also low (1$\times$10-s A/c $m^2$ at $V_{g}$ = +2 V). It is believed that these excellent results were obtained due to existence of the amorphous HfS $i_{x}$/ $O_{y}$ buffer layer. We also investigated the charge trapping characteristics using Fowler-Nordheim electron injection: We found that the degradation of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ gate oxides is more severe when electrons were injected from the gate electrode.e electrode.e.e electrode.e.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
• /
• pp.11-14
• /
• 2003

[ $HfO_2$ ] thin films were deposited at $300^{\circ}C$ on p-type Si (100) substrates using $HfO_2(HfO_xN_y)$ as the precursor by plasma-enhanced chemical vapor deposition and were annealed at $300^{\circ}C$ in nitrogen plasma ambient. Compared with $HfO_2$, nitrogen plasma annealed $HfO_2$ show good chemical stability, higher crystallization temperature, lower leakage current and thermal stability. Leakage current density of nitrogen plasma annealed $HfO_2$ is approximately one order of magnitude lower than that of $HfO_2$ for the same EOT. The improvement in electrical characteristics of nitrogen plasma annealed $HfO_2$ can be explained by the better thermal stability due to nitrogen incorporation.

• 마이크로전자및패키징학회지
• /
• 제11권2호
• /
• pp.29-35
• /
• 2004

65 nm급 게이트 유전체로의 $HfO_2$의 적용을 위해 hydrogen-terminate된 Si 기판과 ECR $N_2$ plasma를 이용하여 SiNx를 형성한 기판 위에 MOCVD를 이용하여 $HfO_2$를 증착하였다. $450^{\circ}C$에서 증착시킨 박막의 경우 낮은 carbon 불순물을 가지며 비정질 matrix에 국부적인 결정화와 가장 적은 계면층이 형성되었으며 이 계면층은 Hf-silicate임을 알 수 있었다. 또한 $900^{\circ}C$, 30초간 $N_2$분위기에서 RTA 결과 $HfO_2/Si$의 single layer capacitor의 경우 계면층의 증가로 인해 EOT가 열처리전(2.6nm)보다 약 1 nm 증가하였다. 그러나 $HfO_2/SiNx/Si$ stack capacitor의 경우 SiNx 계면층은 열처리후에도 일정하게 유지되었으며 $HfO_2$ 박막의 결정화로 열처리전(2.7nm)보다 0.3nm의 EOT 감소를 나타내었으며 열처리후에도 $4.8{\times}10^{-6}A/cm^2$의 매우 우수한 누설전류 특성을 가짐을 알 수 있었다.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2009년도 제38회 동계학술대회 초록집
• /
• pp.381-381
• /
• 2010

$(ZrO_2)_{0.66}(HfO_2)_{0.34}$ thin films as gate dielectrics have been proposed to overcome the problems of tunneling current and degradation mobility inachieving a thin equivalent oxide thickness. An extremely thin $SiO_2$ layer is used in order to separate the carrier in MOSFET channel from the dielectric field fluctuation caused by phonons in the dielectric which decreases the carrier mobility. The electronic and optical properties influenced the device performance to a great extent. $(ZrO_2)_{0.66}(HfO_2)_{0.34}$ dielectric films on p-Si (100) were grown by atomic layer deposition method, for which the conduction band offsets, valence band offsets and band gapswere obtained by using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy. The band gap, valence and conduction band offset values for $(ZrO_2)_{0.66}(HfO_2)_{0.34}$ dielectric thin film, grown on Si substrate were about 5.34, 2.35 and 1.87 eV respectively. This band alignment was similar to that of $ZrO_2$. In addition, The dielectric function (k, $\omega$), index of refraction n and the extinction coefficient k for the $(ZrO_2)_{0.66}(HfO_2)_{0.34}$ thin films were obtained from a quantitative analysis of REELS data by comparison to detailed dielectric response model calculations using the QUEELS-$\varepsilon$(k, $\omega$)-REELS software package. These optical properties are similar with $ZrO_2$ dielectric thin films.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2009년도 하계학술대회 논문집
• /
• pp.104-104
• /
• 2009

Critical dimensions has rapidly shrunk to increase the degree of integration and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate insulator layer and the low conductivity characteristic of poly-silicon. To cover these faults, the study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$ and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-silicon gate is not compatible with high-k materials for gate-insulator. To integrate high-k gate dielectric materials in nano-scale devices, metal gate electrodes are expected to be used in the future. Currently, metal gate electrode materials like TiN, TaN, and WN are being widely studied for next-generation nano-scale devices. The TaN gate electrode for metal/high-k gate stack is compatible with high-k materials. According to this trend, the study about dry etching technology of the TaN film is needed. In this study, we investigated the etch mechanism of the TaN thin film in an inductively coupled plasma (ICP) system with $O_2/BCl_3/Ar$ gas chemistry. The etch rates and selectivities of TaN thin films were investigated in terms of the gas mixing ratio, the RF power, the DC-bias voltage, and the process pressure. The characteristics of the plasma were estimated using optical emission spectroscopy (OES). The surface reactions after etching were investigated using X-ray photoelectron spectroscopy (XPS) and auger electron spectroscopy (AES).

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
• /
• pp.477-477
• /
• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• 한국진공학회지
• /
• 제19권1호
• /
• pp.14-21
• /
• 2010

Ge은 Si에 비하여 높은 이동도를 갖기 때문에 차세대 고속 metal oxide semiconductor field effect transistors (MOSFETs) 소자를 위한 channel 물질로서 각광받고 있다. 그러나 화학적으로 안정한 게이트 산화막의 부재는 MOS 소자에 Ge channel의 사용에 주요한 장애가 되어왔다. 특히, Ge 기판 위에 고품질의 계면 특성을 갖는 게이트 절연막의 제조는 필수 요구사항이다. 본 연구에서, $HfO_xN_y$ 박막은 Ge 기판 위에 플라즈마 원자층 증착법(plasma-enhanced atomic layer deposition, PEALD)을 이용하여 증착되었다. 플라즈마 원자층 증착공정 동안에 질소는 질소, 산소 혼합 플라즈마를 이용한 in situ 질화법에 의하여 첨가되었다. 산소 플라즈마에 대한 질소 플라즈마의 첨가로 성분비를 조절함으로써 전기적 특성과 계면 성질을 향상시키는데 초점을 맞추어서 연구를 진행하였다. 질소 산소의 비가 1：1이었을 때, EOT의 값의 10% 감소를 갖는 고품질의 소자특성을 보여주었다. X-ray photoemission spectroscopy (XPS)와 high resolution transmission electron microscopy (HR-TEM)를 사용하여 박막의 화학적 결합 구조와 미세구조를 분석하였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2010년도 하계학술대회 논문집
• /
• pp.11-11
• /
• 2010

Thin-film-transistors (TFTs) that can be deposited at low temperature have recently attracted lots of applications such as sensors, solar cell and displays, because of the great flexible electronics and transparent. Transparent and flexible transistors are being required that high mobility and large-area uniformity at low temperature [1]. But, unfortunately most of TFT structures are used to be $SiO_2$ as gate dielectric layer. The $SiO_2$ has disadvantaged that it is required to high driving voltage to achieve the same operating efficiency compared with other high-k materials and its thickness is thicker than high-k materials [2]. To solve this problem, we find lots of high-k materials as $HfO_2$, $ZrO_2$, $SiN_x$, $TiO_2$, $Al_2O_3$. Among the High-k materials, $Al_2O_3$ is one of the outstanding materials due to its properties are high dielectric constant ( ~9 ), relatively low leakage current, wide bandgap ( 8.7 eV ) and good device stability. For the realization of flexible displays, all processes should be performed at very low temperatures, but low temperature $Al_2O_3$ grown by sputtering showed deteriorated electrical performance. Further decrease in growth temperature induces a high density of charge traps in the gate oxide/channel. This study investigated the effect of growth temperatures of ALD grown $Al_2O_3$ layers on the TFT device performance. The ALD deposition showed high conformal and defect-free dielectric layers at low temperature compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : $HNO_3$ = 3:1, $Al_2O_3$ layer was deposited by ALD at various growth temperatures or lift-off process. Amorphous InGaZnO channel layers were deposited by rf magnetron sputtering at a working pressure of 3 mTorr and $O_2$/Ar (1/29 sccm). The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. The TFT devices were heat-treated in a furnace at $300^{\circ}C$ and nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B), and LCR meter.