• 한국전기전자재료학회논문지
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• 제29권3호
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• pp.135-140
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• 2016

In this study, we developed the solution-processed PMMA-$HfO_x$ hybrid ReRAM devices to overcome the respective drawbacks of organic and inorganic materials. The performances of PMMA-$HfO_x$ hybrid ReRAM were compared to those of PMMA- and $HfO_x$-based ReRAMs. Bipolar resistive switching behavior was observed from these ReRAMs. The PMMA-$HfO_x$ hybrid ReRAMs showed a larger operation voltage margin and memory window than PMMA-based and $HfO_x$-based ReRAMs. The reliability and electrical instability of ReRAMs were remarkably improved by blending the $HfO_x$ into PMMA. An Ohmic conduction path was commonly generated in the LRS (low resistance state). In HRS (high resistance state), the PMMA-based ReRAM showed SCLC (space charge limited conduction). the PMMA-$HfO_x$ hybrid ReRAM and $HfO_x$-based ReRAM revealed the Pool-Frenkel conduction. As a result of flexibility test, serious defects were generated in $HfO_x$ film deposited on PI (polyimide) substrate. On the other hand, the PMMA and PMMA-$HfO_x$ films showed an excellent flexibility without defect generation.

• 전자공학회논문지
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• 제50권2호
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• pp.98-103
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• 2013

본 연구에서는 IZO를 활성층으로 하고 $HfSiO_x$를 절연층으로 한 TFT에 대하여 그 성능을 측정하였다. $HfSiO_x$는 $HfO_2$ target과 Si target을 co-sputtering 하여 증착하였으며 RF power를 달리 하여 네 가지의 $HfSiO_x$ 박막을 제작하였다. 공정의 간소화를 위해 게이트 전극을 제외한 모든 층들은 RF-magnetron sputtering system과 shadow mask만을 이용하여 증착하였으며 공정의 간소화를 위해 어떠한 열처리도 하지 않았다. 네 가지 $HfSiO_x$ 박막의 구조적 변화를 X-ray diffraction(XRD), atomic force microscopy(AFM)을 통해 분석하였고, 그 전기적 특성을 확인하였다. 박막 내 $HfO_2$와 Si의 조성비에 따라 그 특성이 현저히 차이가 남을 확인하였다. $HfO_2$(100W)-Si(100W)의 조건으로 증착한 $HfSiO_x$ 박막을 절연층으로 한 소자의 특성이 전류 점멸비 5.89E+05, 이동도 2.0[$cm^2/V{\cdot}s$], 문턱전압 -0.5[V], RMS 0.263[nm]로 가장 좋은 결과로 나타났다. 따라서 $HfSiO_x$ 박막 내의 적절한 $HfO_2$와 Si의 조성비가 계면의 질을 향상시킴은 물론, $HfO_2$자체의 trap이나 defect를 효과적으로 줄여 줌으로써 소자의 성능 향상에 중요한 요소라 판단된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.45-49
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• 2001

We have investigated physical and electrical properties of the Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin film for alternative gate dielectrics in the metal-oxide-semiconductor device. The oxidation of Hf deposited directly on the Si substrate results in the H $f_{x}$/ $O_{y}$ interfacial layer and the high-k Hf $O_2$film simultaneously. Interestingly, the post-oxidation N2 annealing of the H102/H1Si70y thin films reduces(increases) the thickness of an amorphous HfS $i_{x}$/ $O_{y}$ layer(Hf $O_2$ layer). This phenomenon causes the increase of the effective dielectric constant, while maintaining the excellent interfacial properties. The hysteresis window in C-V curves and the midgap interface state density( $D_{itm}$) of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin films less than 10 mV and ~3$\times$10$^{11}$ c $m^{-2}$ -eV without post-metallization annealing, respectively. The leakage current was also low (1$\times$10-s A/c $m^2$ at $V_{g}$ = +2 V). It is believed that these excellent results were obtained due to existence of the amorphous HfS $i_{x}$/ $O_{y}$ buffer layer. We also investigated the charge trapping characteristics using Fowler-Nordheim electron injection: We found that the degradation of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ gate oxides is more severe when electrons were injected from the gate electrode.e electrode.e.e electrode.e.

• 한국전기전자재료학회논문지
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• 제22권2호
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• pp.101-106
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• 2009

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

• 마이크로전자및패키징학회지
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• 제15권4호
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• pp.25-29
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• 2008

Reliability and performance in metal gate/high-k device with multiple gate dielectrics were investigated. MOSFETs with a thin $HfSiO_x$ layer on a thermal Si02 dielectric as gate dielectrics exhibit excellent mobility and low interface trap density. However, the distribution of threshold voltages of $HfSiO_x/SiO_2$ stack devices were wider than those of $SiO_2$ and $HfSiO_x$ single layer devices due to the penetration of Hf and/or intermixing of $HfSiO_x$ with underlying $SiO_2$. The results of TZDB and SILC characteristics suggested that a certain portion of $HfSiO_x$ layer reacted with the underlying thick $SiO_2$ layer, which in turn affected the reliability characteristics.

• Transactions on Electrical and Electronic Materials
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• 제4권3호
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• pp.34-37
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• 2003

[ $HfO_2$ ] and $HfO_xN_y$ films were deposited by plasma-enhanced chemical vapor deposition using $Hf[OC(CH_3)_3]_4$ as the precursor in the absence of $O_2$. The crystallization temperature of the $HfO_xN_y$ films is higher than that of the $HfO_2$ film. Nitrogen incorporation in $HfO_xN_y$ was confirmed by auger electron spectroscopy analysis. After post deposition annealing (PDA) at 800$\Box$, the EOT increased from 1.34 to 1.6 nm in the $HfO_2$ thin films, whereas the increase of EOT was suppressed to less than 0.02 nm in the $HfO_xN_y$. The leakage current density decreased from 0.18 to 0.012 $A/cm^2$ with increasing PDA temperature in the $HfO_2$ films. But the leakage current density of $HfO_xN_y$ does not vary with increasing PDA temperature because an amorphous $HfO_xN_y$ films suppresses the diffusion of oxygen through the gate dielectric.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.54-57
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• 2003

[ $HfO_xN_y$ ] films using a hafnium tertiary-butoxide $(Hf[OC(CH_3)_3]_4)$ in plasma and $N_2$ ambient were prepared to improve the thermal stability of hafnium-based gate dielectrics. A 10% nitrogen incorporation into $HfO_2$ films showed a smooth surface morphology and a crystallization temperature as high as $200^{\circ}C$ compared with pure $HfO_2$ films. The $TaN/HfO_xN_y/Si$ capacitors showed a stable capacitance-voltage characteristics even at post-metal annealing temperature of $1000^{\circ}C$ in $N_2$ ambient and a constant value of 1.6 nm EOT (equivalent oxide thickness) irrespective of an increase of PDA and PMA temperature. Leakage current densities of $HfO_xN_y$ capacitors annealed at PDA temperature of 800 and $900^{\circ}C$, respectively were approximately one order of magnitude lower than that of $HfO_2$ capacitors.

• 대한전자공학회논문지SD
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• 제44권5호
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• pp.8-14
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• 2007

본 논문에서는 MOS 소자의 게이트 유전체로 사용될 고유전 박막으로 $HfO_2$/Hf 박막을 제조하여 그 전기적 특성을 관찰하였다. $HfO_2$박막은 TEMAH와 $O_3$ 전구체를 사용한 ALD 방법으로 p-type (100) 실리콘 웨이퍼 위에 증착하였다. $HfO_2$막을 증착시키기 전에 중간층으로써 Hf 금속 층을 증착하였다. Round-type의 MOS 커패시터 제작을 위해, 상부 전극은 Al 또는 Pt을 이용하여 약 2000 ${\AA}$ 두께의 전극을 형성하였다. $HfO_2$ 박막은 화학정량적 특성을 보였으며, $HfO_2$/Si 계면에서 Si-O 결합 대신 Hf-Si 결합과 Hf-Si-O 결합이 관찰되었다. $HfO_2$와 Si 사이의 Hf 중간층은 $SiO_x$의 성장이 억제되었고, $HfSi_xO_y$으로 변형되었다. 이러한 결과로 $HfO_2$/Hf/Si 구조에서 Hf 중간층이 있음으로 게이트 유전체의 고유전율이 유지되면서 계면 특성이 개선됨을 확인하였다.

• 센서학회지
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• 제22권3호
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• pp.233-237
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• 2013

We fabricated electrolyte-insulator-semiconductor (EIS) devices using a solution process and measured the sensing properties of EIS devices according to the thicknesses of sensing membrane. For high pH sensitivity and better stability properties, we used $SiO_2/HfO_x$ (OH) layer as a sensing membrane. In this work, $HfO_x$ sensing membranes were deposited on 5 nm thick $SiO_2$ buffer layer by spin coater with thicknesses of 15, 31, 42, 55 nm, respectively. As a result, we founded that the thickness of $HfO_x$ sensing membrane affects to sensitivity and chemical stability of EIS device. Especially, the EIS device with 42 nm thick $HfO_x$ membrane showed superior sensing ability in terms of pH-sensitivity, linearity, hysteresis voltage and drift rate characteristics than the other devices. In conclusion, we confirmed that it is possible to improve the sensing ability and the chemical stability properties using optimized thickness of sensing membrane and proper annealing process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.275-277
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• 2003

최근 logic 소자의 gate oxide로 기존의 $SiO_2$, SiON보다 고유전, 작은 누설전류를 가지는 물질의 개발이 중요한 이슈가 되고 있다. 본 실험실에서는 Si 기판위에 $HfO_2$를 바로 증착하는 경우, 기판의 Si이 박막내로 확산하여 유전율이 저하되는 문제점을 인식하고, 기판과 $HfO_2$ 사이에 $AlO_x$를 방지막으로 사용하였다. 이 때, $AlO_x$의 Al precursor는 TMA로 고정하고, 산화제로는 $H_2O$, $O_2$-plasma, $O_3$를 각각 사용하였다. 모든 $AlO_x/\;HfO_y$ 박막에서 매우 우수한 누설전류특성을 얻을 수 있었는데, 특히 $O_3$를 산화제로 사용한 $AlO_x$방지막의 경우 가장 우수한 특성을 보였다. 또한 질소 분위기에서 $800^{\circ}C$ 10분간 열처리한 후, 방지막을 사용한 모든 경우에서 보다 향상된 열적 안정성을 관찰할 수 있었다.