• 대한수학회논문집
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• 제32권2호
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• pp.305-319
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• 2017

Recently many authors have investigated so-called Aleph (${\aleph}$)-function and its various properties. Here, in this paper, we aim at establishing certain integral formulas involving the Aleph (${\aleph}$)-function. Precisely, integrals with product of Aleph (${\aleph}$)-function with Jacobi polynomials, Bessel Maitland function, general class of polynomials were under consideration. Some interesting special cases of our main result are also considered and shown to be connected with certain known ones.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권9호
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• pp.412-417
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• 2003

In this Paper, we propose a time-domain magnetic field integral equation (TD-MFIE) formulation for analyzing the transient electromagnetic response from three-dimensional (3-D) dielectric bodies. The solution method in this paper is based on the Galerkin's method that involves separate spatial and temporal testing procedures. Triangular patch basis functions are used for spatial expansion and testing functions for arbitrarily shaped 3-D dielectric structures. The time-domain unknown coefficients of the equivalent electric and magnetic currents are approximated tv a set of orthonormal basis function that is derived from the Laguerre polynomials. These basis functions are also used for the temporal testing. Numerical results computed by the proposed method are presented and compared.

• 한국해양공학회지
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• 제9권1호
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• pp.111-119
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• 1995

The elastic-plastic fracture toughness($J_{IC}$) and fracture resistance (J-R curve) of SA508-3 alloy steel used for nuclear reactor pressure vessel are investigated by using CT-type specimens. Fracture toughness tests are conducted by unloading compliance method and multiple specimen method at room temperature, -2$0^{\circ}C$ and 20$0^{\circ}C$. The apparent negative crack growth phenomenon which usually arises in partial unloading compliance test is well known. The negative crack growth phenomenon in determining J sub(IC) or J-R cure from partial unloading compliance experiments may be eliminated by the offset technique. In this study, the evaluation of $J_{IC}$ multiple specimen method recommended by the JSME gives the most reliable results by using half-size CT(similar-type) specimens.

• Korean Journal of Mathematics
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• 제23권1호
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• pp.47-64
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• 2015

We express generalized Fourier-Feynman transform and convolution product of functionals in a Banach algebra $\mathcal{S}(L^2_{a,b}[0,T])$ as limits of function space integrals on $C_{a,b}[0,T]$. Moreover we obtain change of scale formulas for function space integrals related with generalized Fourier-Feynman transform and convolution product of these functionals.

• Journal of Mechanical Science and Technology
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• 제18권3호
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• pp.357-369
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• 2004

The purposes of the paper are to analyze the fracture phenomenon by delamination and cracking when the encapsulant of plastic IC package with polyimide coating shows viscoelastic behavior under hygrothermal loading in the IR soldering process and to suggest more reliable design conditions by the approaches of stress analysis and fracture mechanics. The model is the plastic SOJ package with the polyimide coating surrounding chip and dimpled diepad. On the package without cracks, the optimum position and thickness of polyimide coating to decrease the maximum differences of strains at the bonding surfaces of parts of the package are studied. For the model delaminated fully between the chip and the dimpled diepad, C(t)-integral values are calculated for the various design variables. Finally, the optimal values of design variables to depress the delamination and crack growth in the plastic IC package are obtained.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권1호
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• pp.41-46
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• 2004

In this paper, we present a new combined field integral equation (CFIE) formulation for the analysis of electromagnetic scattering from arbitrarily shaped three-dimensional perfectly conducting and piecewise homogeneous dielectric composite body. The conducting/dielectric structures are approximated by planar triangular patches, which have the ability to conform to any geometrical surface. The surface covering the conducting body is replaced by an equivalent surface electric current and the surface of the dielectric by equivalent electric and magnetic currents. The all equivalent currents are approximated in terms of RWG (Rao, Wilton, Glisson) functions. The objective of this paper is to illustrate that the CFIE is a valid methodology in removing defects, which occur at a frequency corresponding to an internal resonance of the structure. Numerical results are presented and compared with solutions obtained using other formulations.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제9권2호
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• pp.71-75
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• 2009

The purpose of this paper is to prove a Jensen type inequality for Choquet integrals with respect to a non-additive measure which was introduced by Choquet [1] and Sugeno [20]; $$\Phi((C)\;{\int}\;fd{\mu})\;{\leq}\;(C)\;\int\;\Phi(f)d{\mu},$$ where f is Choquet integrable, ${\Phi}\;:\;[0,\;\infty)\;\rightarrow\;[0,\;\infty)$ is convex, $\Phi(\alpha)\;\leq\;\alpha$ for all $\alpha\;{\in}\;[0,\;{\infty})$ and ${\mu}_f(\alpha)\;{\leq}\;{\mu}_{\Phi(f)}(\alpha)$ for all ${\alpha}\;{\in}\;[0,\;{\infty})$. Furthermore, we give some examples assuring both satisfaction and dissatisfaction of Jensen type inequality for the Choquet integral.

• 전자공학회논문지C
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• 제34C권6호
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• pp.28-36
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• 1997

In this work, a highly linear video-speed CMOS current-mode digital-to-analog converter (DAC) is proposed. A newswitching scheme for the current cell matrix of the DAC simultaneously reduces graded and symmetrical errors to improve integral nonlinearities (INL). The proposed DAC is designed to operate at any supply voltage between 3V and 5V, and minimizes the glitch energy of analog outputs with degliching circuits developed in this work. The prototype dAC was implemented in a LG 0.8um n-well single-poly double-metal CMOS technology. Experimental results show that the differential and integral nonlinearities are less than .+-. LSB and .+-.0.8LSB respectively. The DAC dissipates 75mW at a 3V single power supply and occupies a chip area of 2.4 mm * 2.9mm.

• 대한수학회논문집
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• 제20권2호
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• pp.339-350
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• 2005

We obtain the following two inequalities on a strongly pseudoconvex domain $\Omega\;in\;\mathbb{C}^n\;:\;for\;f\;{\in}\;O(\Omega)$ $$\int_{0}^{{\delta}0}t^{a{\mid}a{\mid}+b}M_p^a(t, D^{a}f)dt\lesssim\int_{0}^{{\delta}0}t^{b}M_p^a(t,\;f)dt\;\int_{O}^{{\delta}O}t_{b}M_p^a(t,\;f)dt\lesssim\sum_{j=0}^{m}\int_{O}^{{\delta}O}t^{am+b}M_{p}^{a}\(t,\;\aleph^{i}f\)dt$$. In [9], Shi proved these results for the unit ball in $\mathbb{C}^n$. These are generalizations of some classical results of Hardy and Littlewood.

• 대한전자공학회논문지SD
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• 제44권4호
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• pp.43-54
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• 2007

본 논문에서는 실시간 처리를 위한 얼굴 검출 알고리즘의 하드웨어 엔진을 설계하고 검증하였다. 얼굴 검출 알고리즘은 주어진 이미지에서 학습된 얼굴의 특징데이터를 통하여 얼굴의 대략적인 위치를 찾는 연산을 수행한다. 얼굴 검출 알고리즘을 하드웨어 구조로 설계하기 위해 Integral Image Calculator, Feature Coordinate Calculator, Feature Difference Calculator, Cascade Calculator, Window Detector 등의 5 단계로 구조를 나누었으며, On-Chip Integral Image memory 와 Feature Parameter Memory를 설계하였다. 삼성전자의 S3C2440A 프로세서 칩과 Xilinx사의 Virtex4LX100을 이용하여 검증 플랫폼을 구축하고, CCD카메라를 통하여 실제 얼굴의 영상을 받아들여 얼굴 검출을 실시간으로 구동시켜 검증하였다. 설계된 하드웨어는 Virtex4LX100 FPGA를 타겟으로 합성 시에 3,251 LUTs 를 사용하고, 24MHz의 동작 속도에서 검색 윈도우의 이동 간격에 따라 프레임 당 1.96$\sim$0.13 초의 실행속도를 가진다. 그리고 매그나칩 0.25um ASIC 공정으로 제작 시 41만 게이트 (Combinational area 약 34.5만 게이트, Noncombinational area 약 6.5만 게이트)의 크기를 가지며, 100MHz의 동작 속도에서 프레임 당 0.5초 미만의 실행 속도로, 임베디드 시스템의 실시간 얼굴 검출 솔루션에 적합함을 보여준다. 실제 XF1201칩의 일부 모듈로 구현되어 동작함이 확인되었다.