• 소성∙가공
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• 제15권3호
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• pp.195-205
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• 2006

This paper focuses on a rheo-forming of am part fabricated by electromagnetic stirring system (EMS). This forming process take place under high pressure of high pressure die casting and thin walled casting is possible. Furthermore, the productivity is better than low pressure die casting because of shorter cycle time. The advantages of rheo-forming are performed in the semi solid state with laminar flow and the gas content is low, which makes welding possible. Therefore this research applies for arm part with EMS and has investigated the mechanical properties after T6 and T5 heat-treatment.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.123-123
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• 2000

선폭이 초미세화됨에 따라 게이트 전극에서의 공핍 현상 및 불순물 확산의 물제를 갖는 poly-Si 게이트를 대체할 전극 물질로 텅스텐(W)이 많이 연구되어 왔다. 반도체 소자의 배선물질로 일찍부터 사용되어온 텅스텐은 내화성 금속의 일종으로 용융점이 높고, 저항이 낮다. 그러나, 일반적으로 사용되고 있는 CVD에 의한 텅스텐의 증착은 반응가스(WF6)로부터 오는 불소(F)의 게이트 산화막내로의 확산으로 인해 MOS 소자가 크게 열화될수 있다. 본 연구에서는 W/TiN 이중 게이트 전극 구조를 갖는 MOS 캐패시터를 제작하여 전기적 특성을 살펴보았다. P-Type (100) Si위에 RTP를 이용, 85$0^{\circ}C$에서 110 의 열산화막을 성장 및 POA를 수행한 후, 반응성 스퍼터링법에 의해 상온, 6mTorr, N2/Ar=1/6 sccm, 100W 조건에서 TiN 박막을 150, 300, 500 의 3그룹으로 증착하였다. 그 위에 LPCVD 방법으로 35$0^{\circ}C$, 0.7Torr, WF6/SiH4/H2=5/5~10/500sccm 조건에서 2000~3000 의 텅스텐을 증착하였다. Photolithography 공정 및 습식 에칭을 통해 200$\mu\textrm{m}$$\times$200$\mu\textrm{m}$ 크기의 W/TiN 복층 게이트 MOSC를 제작하였다. W/TiN 복측 게이트 소자와 비교분석하기 위해 같은 조건의 산화막을 이용한 알루미늄(Al) 게이트, 텅스텐 게이트 MOSC를 제작하였다. 35$0^{\circ}C$에서 증착된 텅스텐 박막은 10~11$\Omega$/ 의 면저항을 가졌고 미소한 W(110) peak값을 나타내는 것으로 보아 비정질 상태에 가까웠다. TiN 박막의 경우 120~130$\Omega$/ 의 면저항을 가졌고 TiN (200)의 peak 값이 크게 나타난 반면, TiN(111) peak가 미소하게 나타났다. TiN 박막의 두께와 WF/SiH4의 가스비를 변화시켜가며 제작된 MOS 캐패시터를 HF 및 QS C-V, I-V 그리고 FNT를 통한 전자주입 방법을 이용하여 TiN 박막의 불소에 대한 확산 방지막 역할을 살펴 보았다. W/TiN 게이트 MOS 소자는 모두 순수 텅스텐 게이트보다 우수하였고, Al 게이트와 유사한 전기적 특성을 보여주었다. W/TiN 게이트 MOS 소자는 모두 순수 텅스텐 게이트보다 우수하였고, Al 게이트와 유사한 전기적 특성을 보여주었다. TiN 박막이 300 , 500 이고 WF6/SiH4의 가스비가 5:10인 경우 소자 특성이 우수하였으나, 5:5의 경우에는 FNT 전자주입 특성이 열화되기 시작하였다. 그리고, TiN박막의 두께가 150 으로 얇아질 경우에는 WF6/SiH4의 가스비가 5:10인 경우에서도 소자 특성이 열화되기 시작하였다. W/TiN 복층 게이트 MOS 캐패시터를 제작하여 전기적인 특성 분석결과, 순수 텅스텐 게이트 소자의 큰 저전계 누설 전류 특성을 해결할 수 있었으며, 불소확산에 영향을 주는 조건이 WF6/SiH4의 가스비에 크게 의존됨을 알 수 있었다. TiN 박막의 증착 공정이 최적화 될 경우, 0.1$\mu\textrm{m}$이하의 초미세소자용 게이트 전극으로서 텅스텐의 사용이 가능할 것으로 보여진다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 C
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• pp.1555-1558
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• 2002

This paper presents deposition and characterizations of microcrystalline silicon(${\mu}c$-Si:H) films prepared by hot wire chemical vapor deposition at substrate temperature below $300^{\circ}C$. The $SiH_4$ Concentration$[F(SiH_4)/F(SiH_4)+F(H_2)]$ is critical parameter for the formation of Si films with microcrystalline phase. At 6% of silane concentration, deposited intrinsic ${\mu}c$-Si:H films shows sufficiently low dark conductivity and high photo sensitivity for solar cell applications. P-type ${\mu}c$-S:H films deposited by Hot-Wire CVD also shows good electrical properties by varying the rate of $B_2H_6$ to $SiH_4$ gas. The solar cells with structure of Al/nip ${\mu}c$-Si:H/TCO/glass was fabricated with sing1e chamber Hot-Wire CVD. About 3% solar efficiency was obtained and applicability of HWCVD for thin film solar cells was proven in this research.

• Current Photovoltaic Research
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• 제2권1호
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• pp.1-7
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• 2014

We developed a method of growing thin Si film at $600^{\circ}C$ by hot wire CVD using a very thin large-grained poly-Si seed layer for thin-film Si solar cells. The seed layer was prepared by crystallizing an amorphous Si film by vapor-induced crystallization using $AlCl_3$ vapor. The average grain size of the p-type epitaxial Si layer was about $20{\mu}m$ and crystallographic defects in the epitaxial layer were mainly low-angle grain boundaries and coincident-site lattice boundaries, which are special boundaries with less electrical activity. Moreover, with a decreasing in-situ boron doping time, the mis-orientation angle between grain boundaries and in-grain defects in epitaxial Si decreased. Due to fewer defects, the epitaxial Si film was high quality evidenced from Raman and TEM analysis. The highest mobility of $360cm^2/V{\cdot}s$ was achieved by decreasing the in-situ boron doping time. The performance of our preliminary thin-film solar cells with a single-side HIT structure and $CoSi_2$ back contact was poor. However, the result showed that the epitaxial Si film has considerable potential for improved performance with a reduced boron doping concentration.

• Journal of information and communication convergence engineering
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• 제1권4호
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• pp.199-204
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• 2003

In this paper, we present the thermal annealing effects of the W/$SiO_2$ multi-layer reflectors in ZnO-based FBAR devices with cobalt (Co) electrodes in comparison with those with aluminum (Al) electrodes. Various thermal annealing conditions have been implemented on the W/$SiO_2$ multi-layer reflectors formed on p-type (100) silicon substrates. The resonance characteristics could be significantly improved due to the thermal annealing and were observed to depend strongly on the annealing conditions applied to the reflectors. Particularly, the FBAR devices with the W/$SiO_2$ multi- layer reflectors annealed at $400^{\circ}C$/30min have shown superior resonance characteristics in terms of return loss and quality-factor (Q-factor). In addition, the use of Co electrodes has resulted in further improvement of the resonance characteristics as compared with the Al electrodes. As a result, the combined use of both the thermal annealing and Co electrodes seems very useful to more effectively improve the resonance characteristics of the FBAR devices with the W/$SiO_2$ multi-layer reflectors.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 대한수학회논문집
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• 제38권3호
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• pp.695-704
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• 2023

Area problems for triangles and polygons whose vertices have Fibonacci numbers on a plane were presented by A. Shriki, O. Liba, and S. Edwards et al. In 2017, V. P. Johnson and C. K. Cook addressed problems of the areas of triangles and polygons whose vertices have various sequences. This paper examines the conditions of triangles and polygons whose vertices have Lucas sequences and presents a formula for their areas.

• 구강회복응용과학지
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• 제21권1호
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• pp.33-42
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• 2005

This study was performed to investigate the surface properties and in vitro biocompatibility of electrochemically oxidized Ti-6Al-7Nb alloy by anodic spark discharge technique. Discs of Ti-6Al-7Nb alloy of 20 mm in diameter and 2 mm in thickness were polished sequentially from #300 to 1000 SiC paper, ultrasonically washed with acetone and distilled water for 5 min, and dried in an oven at $50^{\circ}C$ for 24 hours. Anodizing was performed using a regulated DC power supply. The applied voltages were given at 240, 280, 320, and 360 V and current density of $30mA/cm^2$. Hydrothermal treatment was conducted by high pressure steam at $300^{\circ}C$ for 2 hours using a autoclave. Samples were soaked in the Hanks' solution with pH 7.4 at $36.5^{\circ}C$ during 30 days. The results obtained were summarized as follows; 1. The oxide films were porous with pore size of $1{\sim}5{\mu}m$. The size of micropores increased with increasing the spark forming voltage. 2. The main crystal structure of the anodic oxide film was anatase type as analyzed with thin-film X-ray diffractometery. 3. Needle-like hydroxyapatite (HA) crystals were observed on anodic oxide films after hydrothermal treatment at $300^{\circ}C$ for 2 hours. The precipitation of HA crystals was accelerated with increasing the spark forming voltage. 4. The precipitation of the fine asperity-like HA crystals were observed after being immersed in Hanks' solution at $37^{\circ}C$. The precipitation of HA crystals was accelerated with increasing the spark forming voltage and the time of immersion in Hanks' solution. 5. The Ca/P ratio of the precipitated HA layer was equivalent to that of HA crystal as increasing the spark forming voltage and the time of immersion in Hanks' solution.

• 구강회복응용과학지
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• 제22권1호
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• pp.101-110
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• 2006

This study was performed to investigate the surface properties and in vitro biocompatibility of electrochemically oxidized Ti-6Al-7Nb alloy by anodic spark discharge technique. Discs of Ti-6Al-7Nb alloy of 20 mm in diameter and 2 mm in thickness were polished sequentially from #300 to 1000 SiC paper, ultrasonically washed with acetone and distilled water for 5 min, and dried in an oven at $50^{\circ}C$ for 24 hours. Anodizing was performed using a regulated DC power supply. The applied voltages were given at 240, 280, 320, and 360 V and current density of $30mA/cm^2$. Hydrothermal treatment was conducted by high pressure steam at $300^{\circ}C$ for 2 hours using a autoclave. Samples were soaked in the Hanks' solution with pH 7.4 at $36.5^{\circ}C$ during 30 days. The results obtained were summarized as follows; 1. The oxide films were porous with pore size of $1{\sim}5{\mu}m$. The size of micropores increased with increasing the spark forming voltage. 2. The main crystal structure of the anodic oxide film was anatase type as analyzed with thin-film X-ray diffractometery. 3. Needle-like hydroxyapatie (HA) crystals were observed on anodic oxide films after hydrothermal treatment at $300^{\circ}C$ for 2 hours. The precipitation of HA crystals was accelerated with increasing the spark forming voltage. 4. The precipitation of the fine asperity-like HA crystals were observed after being immersed in Hanks' solution at $37^{\circ}C$. The precipitation of HA crystals was accelerated with increasing the spark forming voltage and the time of immersion in Hanks' solution. 5. The Ca/P ration of the precipitated HA layer was equivalent to that of HA crystal as increasing the spark forming voltage and the time of immersion in Hanks' solution.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.396-399
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• 2003

4H-SiC un diodes with field limiting rings(FLRs) were fabricated and characterized. The dependences of reverse breakdown voltage on the number of FLRs, the distance between p-base main junction and first FLR, and activation temperatures, were investigated. Al and B ions were implanted and activated at high temperature to form p-base region and p+ region in the n-epilayer. We have obtained up to 1782V of reverse breakdown voltage in the un diode with two FLRs on loom thick epilayer. The differential on-resistances of the fabricated diode are $5.3m{\Omega}cm^2$ at $100A/cm^2$ and $2.7m{\Omega}cm^2$ at $1kA/cm^2$, respectively. All pn diodes with FLRs have higher avalanche breakdown voltages than that of diode without an FLR. Regardless of the activation temperature, the un diode with a FLR located 5um apart from main junction has the highest mean breakdown voltage around 1600V among the diodes with one ring. On the other hand, the pn diode with two rings showed different behavior with activation temperature. It reveals that high voltage SiC pn diodes with low on-resistance can be fabricated by using the FLR edge termination.