• 열처리공학회지
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• 제25권2호
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• pp.74-79
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• 2012

This study has been carried out to investigate the precipitation behavior of ${\chi}$ phase and effect of ${\chi}$ phase precipitation on the impact toughness of 25%Cr-7%Ni-4%Mo super duplex stainless steel. It was proved that the ${\chi}$ phase was a intermetallic compound, which represented the higher chromium and molybdenum concentration than the matrix phases, and also showed the higher molybdenum concentration than the ${\sigma}$ phase. The ${\chi}$ phase was precipitated at the interface between ferrite and austenite or inside the ferrite matrix in the early stage of aging. The number of ${\chi}$ phase precipitates increased with increasing aging time, however, after showing the maximum value, the number was decreased due to the gradual transformation of ${\chi}$ phase into ${\sigma}$-phase. Aging ferrite phase was decomposed by the $r^2$ phase and ${\sigma}$-phase. Impact toughness rapidly decreased with time in the initial stage of aging at ${\chi}$ phase start to precipitate. Thus, the impact toughness was greatly influence for the precipitation of ${\chi}$ phase.

• 한국품질경영학회:학술대회논문집
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• 한국품질경영학회 2006년도 추계 학술대회
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• pp.157-163
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• 2006

There are big differences in six sigma applications between manufacturing processes and transactional processes. This paper analyzes the differences between two areas by examining 18 six sigma case studies in Korean companies. To characterize six sigma cases, a step-by-step checklist is developed based on 12-step DMAIC methodology proposed by US six sigma academy. On the basis of those characterized data, the differences between two areas are analyzed. The most significant differences is that statistical tools are widely used in manufacturing processes, but qualitative tools are used in transactional processes during improvement phase.

• 한국해양공학회지
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• 제27권2호
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• pp.75-79
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• 2013

This study was carried out to investigate the precipitation behavior of the ${\chi}$ phase and the impact toughness of 25%Cr-7%Ni-2%Mo-4%W super duplex stainless steel. The ${\chi}$ phase was precipitated in the early stage of aging, and with the increasing aging time. However, after reaching a maximum value, the number decreased as a result of the gradual transformation of the ${\chi}$ phase into the ${\sigma}$-phase. It was proved that the ${\chi}$ phase was an intermetallic compound, which represented a lower nickel concentration, higher chromium and molybdenum concentrations, and very higher tungsten concentration compared to the matrix phases. It also showed higher molybdenum and tungsten concentrations than the ${\sigma}$ phase. The decomposition of the ferrite phase into the ${\gamma}_2$ and ${\sigma}$ phases was retarded by W substitution for Mo. Thus, the number of ${\chi}$ phases increased. The impact value was decreased by the substitution of W for Mo. The impact toughness rapidly decreased with time when the ${\chi}$ phase began to precipitate in the initial stage of aging. The impact toughness was, therefore, greatly influenced for the precipitation of the ${\chi}$ phase.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.425-435
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• 2016

This paper describes a spread-spectrum clock generation method by utilizing a ${\Delta}{\Sigma}$ digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order ${\Delta}{\Sigma}$ modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The ${\Delta}{\Sigma}$ DPLL employs a two-point modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 GHz spread-spectrum clock generator (SSCG) is implemented in 65 nm CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 dB and 11 dB with 10 kHz and 100 kHz resolution bandwidths respectively, consuming 6.34 mW from a 1 V supply.

• 한국해양공학회지
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• 제22권4호
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• pp.46-50
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• 2008

Super duplex stainless steel has along life in severe environments because of its strength and corrosion resistance. If 0.2$\sim$0.3% Nitrogen in aninterstitial solid solution is added, the austenite structure is reinforced. This improves the solid solution hardening and the anticorrosionability. In this study, the mechanical properties and structures of the super duplex stainless steel with the 0.2% N additive were investigated to determine the effect of various volume fractions on the austenite phase. The various volume fractions and distributions of the austenite structure in the applied test specimens were obtained by changing the heat treatment temperature and cycle. The characteristics by amounts of the $\sigma$ phase obtained from the precipitation heat treatment were alsoinvestigated. From the results, when the austenite volume fraction increases, the tensile strength decreases and elongation increases. And the $\sigma$ phase was rapidly increased by increasing the heat treatment time. When the volume fraction of the $\sigma$ phase increased, tensile strength increased.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.342-348
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• 2015

This paper presents a 1.9-GHz digital ${{\Delta}{\Sigma}}$ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in $0.11-{\mu}m$ CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.

• Bulletin of the Korean Chemical Society
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• 제33권7호
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• pp.2168-2176
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• 2012

Relations between fitted parameters for photoionization spectra both below and above the thresholds in the systems involving 3 channels are obtained using phase-shifted version of the multichannel quantum-defect theory. Analytical continuation of the photoionization cross sections in the form of ${\langle}{\sigma}_{below}{\rangle}_{v_{below}}={\sigma}_{above}$ examined using several representations.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권1호
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• pp.41-48
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• 2002

This paper presents a 18-mW, 2.5-㎓ fractional-N frequency synthesizer with l-bit $4^{th}$-order interpolative delta-sigma ($\Delta{\;}$\sum$)modulator to suppress fractional spurious tones while reducing in-band phase noise. A fractional-N frequency synthesizer with a quadruple prescaler has been designed and implemented in a $0.5-\mu\textrm{m}$ 15-GHz $f_t$ BiCMOS. Synthesizing 2.1 GHzwith less than 200 Hz resolution, it exhibits an in-band phase noise of less than -85 dBc/Hz at 1 KHz offset frequency with a reference spur of -85 dBc and no fractional spurs. The synthesizer also shows phase noise of -139 dBc/Hz at an offset frequency of 1.2 MHz from a 2.1GHz center frequency.

• 품질경영학회지
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• 제40권3호
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• pp.316-326
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• 2012

Purpose: In this paper, a Design for Six Sigma(DFSS) methodology based on DMADV(Define-Measure-Analyze-Design-Verify) roadmap is presented. Methods: DFSS tools are given for each DMADV phase which is suitable for the aircraft development process. A cost reduction case study of a navigation simulation is demonstrated. Results: DFSS roadmap are presented with implementation tools for each phase. Conclusion: We propose a DFSS methodology which can benefit the design and development personnel to implement DFSS not only in aircraft industry but also in other order-based industries in general.

• 대한원격탐사학회지
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• 제17권2호
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• pp.141-153
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• 2001

A semi-empirical polarimetric backscattering model for bare soil surfaces is presented. Based on measurements by using polarimetric scatterometers and the JPL AirSAR, as well as the theoretical models, the backscattering coefficints $\sigma$$^0_w$, $\sigma$$^0_{hh}$ and $\sigma$$^0_{vh}$, and the parameters of the copolarized phase-difference probability density function, namely the degree of correlation $\alpha$ and the copolarized-phase-difference $\zeta$, are modeled empirically in terms of the volumetric soil moisture content m$_v$ and the surface roughness parameters $k_s$ and $k_l$, where k=2$\pi$f/c, s is the rms height and l is the correlation length.