• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.981-986
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• 1992

In order to implement the digital PID control algorithm, it is necessary to consider the effect of the finite word length(FWL). In this paper, we show the FWL effect in the digital PID controllers. The conception analyse the effects of the signal quantization error in the digital PID algorithm and the coefficient wordlength determined from performance criteria with the statistical wordlength concept. Throughout this paper, it is dealt with the type of controller structure based delta operator the delta operator has such advantages are superior rounfoff noise perfoff noise performance, more accurate coefficient repersentation, and less sensitive control law.

• The Sea:JOURNAL OF THE KOREAN SOCIETY OF OCEANOGRAPHY
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• v.10 no.2
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• pp.124-128
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• 2005

Marine reservoir correction $({\Delta}R)$ values are measured using two species of mollusk tests collected by NFRDI in 1942 before nuclear bomb testing to convert the radiocarbon age to calendar age in Korean coastal waters more accurately. The ${\Delta}R$ values are calculated to be $-117\pm45\;^{14}C\;yr$ in the southwestern coast of Korea and $-160\pm35\;^{14}C\;yr$ in southeastern coast. These values are similar to those in Chinese coast of the Yellow Sea $(-81\pm60\~-178\pm50\;^{14}C\;yr$, indicating that regional reservoir $^{14}C$ ages of these areas are lower than mean global reservoir $^{14}C$ age. The lower ${\Delta}R$ values in these areas are presumed to be mainly caused by influence of fresh-water inflow. The ${\Delta}R$ values presented In this study enhance the accuracy in converting radiocarbon age to calendar age in Korean coastal waters.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.4
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• pp.1-8
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• 2010

In this paper, we propose a new gain optimization technique for Sigma-Delta A/D converters. In the proposed scheme, multiple gain set candidates showing maximum SNR in the modulator block are selected, and then multiple gain set candidates are investigated for minimum MSE in decimation block. Through CIC decimation filter simulation, it is shown that second SNR ranking candidate in modulation block is the best gain set.

• Journal of Korean Ophthalmic Optics Society
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• v.10 no.1
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• pp.9-15
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• 2005

The polariscope to measure the microscopic stress in CR lens consists of light source polarizer, model, polarizer, CCD, computer, chrome conversion orderly and the principal-stressed difference, (${\sigma}_1-{\sigma}_2$) and the fringe order n were measured by analyzing two components of light wave $E_1$ and $E_2$ following each polarizer's steps. The two-dimensional model could be determined from the fact that the optical axes of sample concide with the principal-stress directions. The bi-refringence acted to a light wave and the phase retardation were in proportion to the principal-stressed difference(${\sigma}_1-{\sigma}_2$) and the intensity of final light wave was proportioned to $sin2({\Delta}/2)$ and when ${\Delta}/2=n{\pi}$ (n=0, 1, 2, ${\ldots}$) the extinction occurs. Photoelastic's image by microscopic stress could analyzed using chrome conversion, and the image showed clearly.

• Journal of IKEEE
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• v.16 no.1
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• pp.28-33
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• 2012

Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.39-47
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• 1998

A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.2
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• pp.111-117
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• 2004

The low-power design of the A/D converter is indispensable to achieve the compact bio-signal measuring device with long battery duration. In this paper, new decimation filter structure is proposed for the low-power design of the Sigma-Delta A/D converter in the bio-instruments. The proposed filter is based on the non-recursive structure of the CIC (Cascaded Integrator Comb) decimation filter in the Sigma-Delta A/D converter. By combining the CSD (Canonic Signed Digit) structure with common sub-expression sharing technique, the proposed decimation filter structure can significantly reduce the number of adders for implementation. For the fixed decimation factor of 16, the 15％ of power consumption saving is achieved in the proposed structure in comparison with that of the conventional polyphase CIC filter.

• Proceedings of the KAIS Fall Conference
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• 2004.11a
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• pp.174-178
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• 2004

본 논문에서는 일명 델타변환 무정전전원장치(UPS)로서 알려져 있는 3상 라인 인터랙티브 UPS 시스템의 성능 시험에 대해서 다루고 있다. 델타변환 UPS는 종래의 단일 변환 라인 인터랙티브 UPS 시스템에서 직렬 인덕터를 제거하고 직렬 및 병렬 PWM 컨버터를 사용하는 새로운 라인 인터랙티브 UPS 시스템으로 전원 전류를 직접 제어함으로써 UPS 시스템의 입출력 특성들이 상당히 개선되는 것으로 알려져 있다. 여기서는 UPS 시스템의 성능 시험에서 중요한 내용들인 부하시험, 정전/복전시험, 동기절체 시험 등에 대한 결과들을 제시하고 델타변환 UPS 시스템에 대한 전반적인 평가를 한다.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.3
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• pp.165-169
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• 2008

Analog-to-Digital converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental converters provide a solution for such measurement applications, as they retain most of the advantages of conventional ${\Delta}{\Sigma}$ converters, and yet they are capable of offset-free and accurate conversion. Most of the previous research on incremental converters was for single-channel and dc signal applications, where they can perform extremely accurate data conversion with more than 20-bit resolution. In this paper, a design technique for implementing multiplexed incremental data converters to convert narrow bandwidth ac signals is discussed. A design methodology to optimize the signal-to-quantization+thermal noise ratio of multiplexed IDC is presented. It incorporates the operation principle, topology, and digital decimation filter design. The theoretical results are verified by simulation results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.43-49
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• 2004

In this paper, we have designed a mode size converter to reduce coupling loss between super-high delta silica optical waveguides and single mode fibers. The new mode size converter has three design aspects; periodically segmented taper waveguide for minimal size, lateral taper waveguide for simple fabrication, and surrounding trenches to improve coupling loss. In the optimal mode size converter design, coupling loss is 0.33dB/point without trenches and 0.2dB/point with trenches.