• Korean Journal of Materials Research
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• v.13 no.7
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• pp.478-483
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• 2003

The crystallographic characteristics of the $(Bi, La)_4$$Ti_3$$O_{12}$ thin film, which is considered as an applicable dielectrics in the ferroelectric RAM device due to a low crystallization temperature and a good fatigue property, were investigated at the atomic scale by high resolution transmission electron microscopy and the high resolution Z-contrast technique. The analysis showed that a (00c) preferred orientation and a crystallization of the film were enhanced with the diffraction intensity increase of the (006) and (008) plane as the annealing temperature increased. It indicated a change of the atomic arrangement in the (00c) plane. Stacking faults on the (00c) plane were also observed. Through the comparison of the high-resolution Z-contrast image and the $Bi_4$$Ti_3$$O_{12}$ atomic model, it was evaluated that the intensity of the Bi atom was different according to the atomic plane, and it was attributed to a substitution of La atom for Bi at the specific atom position.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.565-568
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• 2001

We have fabricated $Bi_{3.25}La_{0.75}Ti_{3}O_{12}(BLT)$ thin(200nm) films on the $Pt/Ti/SiO_{2}/Si$ substrates using a MOD(Metalorganic decomposition) method with annealing temperature from $550^{\circ}C$ to $750^{\circ}C$. The structural properties of the films examined by x-ray diffraction. The layered-perovskite phase obtained above $600^{\circ}C$. Scanning electron micrographs showed uniform surface composed of rodlike grains. The grain size increased with increasing annealing temperature. The BLT thin films showed little polarization fatigue test up to $3.5{\times}10^{9}$ bipolar cycling at a 5V and 100kHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.565-568
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• 2001

We have fabricated $Bi_{3.25}$$La_{0.75}$ti$_3$O$_{12}$ (BLT) thin(200nm) films on the Pt/Ti/SiO$_2$/Si substrates using a MOD(Metalorganic decomposition) method with annealing temperature from 55$0^{\circ}C$ to 75$0^{\circ}C$. The structural properties of the films examined by x-ray diffraction. The layered-perovskite phase obtained above $600^{\circ}C$. Scanning electron micrographs showed uniform surface composed of rodlike grains. The grain size increased with increasing annealing temperature. The BLT thin films showed little polarization fatigue test up to 3.5x10$^{9}$ bipolar cycling at a 5V and 100kHz.kHz.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.7
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• pp.575-580
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• 2007

A 16 Mb 1T1C FeRAM device was integrated with BLT capacitors. But a lot of cells were failed randomly during the measuring the bit-line signal distribution of each cell. The reason was revealed that the grain size and orientation of the BLT thin film were severely non-uniform. And the grain size and orientation were severely affected by the process conditions of post heat treatment, especially nucleation step. The optimized annealing temperature at the nucleation step was $560^{\circ}C$. The microstructure of the BLT thin film was also varied by the annealing time at the step. The longer process time showed the finer grain size. Therefore, the uniformity of the grain size and orientation could be improved by changing the process conditions of the nucleation step. The FeRAM device without random bit-fail cell was successfully fabricated with the optimized BLT capacitor and the sensing margin in bit-line signal distribution of it was about 340 mV.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.265-271
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• 2003

Ferroelectric lanthanum-substituted Bi$_4$Ti$_3$O$_{12}$(BLT) thin films were fabricated by spin-coating onto a Pt/Ti/SiO$_2$/Si substrate by metalorganic decomposition technique. The grain size in BLT thin films were prepared with controlled by various drying process. The effect of grain size on the crystallization and ferroelectric properties were investigated by x-ray diffraction and field emission scanning electron microscope. The dependence of crystallization and electrical properties are related to the grain size in BLT thin films with different drying temperature. The remanent polarization of BLT thin film increases with the increasing grain size. The value of 2P$_{r}$ and E$_{c}$ of BLT thin film dried at 45$0^{\circ}C$ were 25.9 $\mu$C/$\textrm{cm}^2$ and 85 kV/cm, respectively. The BLT thin film with larger grain size has better fatigue properties. The fatigue properties revealed that small grained film showed more degradation of switching charge than large grained films.lms.s.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.851-856
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• 2003

We have investigated the material and electrical properties of $Bi_{4-x}La_xTi_3O_{12}$ (BLT) ferroelectric thin film for ferroelectric nonvolatile memory applications of capacitor type and single transistor type. The 120nm thick BLT films were deposited on $Pt/Ti/SiO_2/Si$ and $SiO_2/Nitride/SiO_2$ (ONO) substrates by the sol-gel spin coating method and were annealed at $700^{\circ}C$. It was observed that the crystallographic orientation of BLT thin films were strongly affected by the excess Bi content and the intermediate rapid thermal annealing (RTA) treatment conditions regardeless of two type substrates. However, the surface microstructure and roughness of BLT films showed dependence of two different type substrates with orientation of (111) plane and amorphous phase. As increase excess Bi content, the crystallographic orientation of the BLT films varied drastically in BLT films and exhibited well-crystallized phase. Also, the conversion of crystallographic orientation at intermediate RTA temperature of above $450^{\circ}C$ started to be observed in BLT thin films with above excess 6.5% Bi content and the rms roughness of films is decreased. We found that the electrical properties of BLT films such as the P-V hysteresis loop and leakage current were effectively modulated by the crystallographic orientations change of thin films.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.13 no.2
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• pp.56-62
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• 2003

Epitaxial $Bi_4Ti_3O_{12}$ films on $SrTiO_3$(100), L$aA1O_3$(100) and MgO(100) were prepared by sol-gel process using metal naphthenate as a starting material. As-deposited films were pyrolyzed at $500^{\circ}C$ for 10 min In air and annealed at $750^{\circ}C$ for 30 min in air. Crystallinity and in-plane alignment of the film were investigated by X-ray diffraction $\theta$-2$\theta$ scan and P scanning. A field emission-scanning electron microscope and an atomic force microscope were used for characterizing the surface morphology and the surface roughness of the film. The film prepared on MgO(100) showed the most poor crystallinity and in-plane alignment, compared to those on the other substrates. While the films on $LaA1O_3$(100) and $SrTiO_3$(100) having high crystallinity and in-plane alignment showed the form of columnar grain growth, the film on MgO(100) which had poor crystallinity showed the form of acicula grain growth.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.277-277
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• 2007

$(Bi,La)_4Ti_3O_{12}$ (BLT) 물질은 결정 방향에 따른 강한 이방성의 강유전 특성을 나타낸다. 따라서 BLT 박막을 이용하여 FeRAM 소자 등을 제작하기 위해서는 결정의 방향성을 세심하게 제어하는 것이 매우 중요하다. 현재까지 연구된 BLT 박막의 방향성 조절 결과를 보면, BLT 박막을 스핀 코팅 법 (spin coating method)으로 중착하고, 핵생성 열처리 단계를 조절하여 무작위 방향성 (random orientation)을 갖는 박막을 제조하는 방법이 일반적이었다. 그런데 이러한 스핀 코팅법에서의 핵생성 단계의 제어는 공정 조건 확보가 너무 어려운 단점이 있다. 이러한 어려움을 극복할 수 있는 대안은 스퍼터링 증착법 (sputtering deposition method), PLD법 (pulsed laser deposition method) 등과 같은 PVD (physical vapor deposition) 법의 증착방법을 적용하는 것이다. PVD 법으로 증착하는 경우에는 이미 박막 내에 무수한 결정핵이 존재하기 때문에 핵생성 단계가 필요 없게 된다. PVD 증착법의 적용을 위해서는 타겟 (target)의 제조 및 평가 실험이 선행되어야 한다. 그런데 벌크 BLT 재료의 소결공정 조건과 전기적 특성에 관한 연구 결과는 거의 발표 되지 않고 있다. 본 실험에서는 $Bi_2O_3$, $TiO_2$ and $La_2O_3$ 분말을 이용하여 최적의 조성을 구하기 위하여 Bi양을 변화시키며 타겟을 제조 하였다. 혼합된 분말을 하소 후 pallet 형태로 성형하여 소결을 실시하였다. 시편을 1mm 두께로 연마하고, 표면에 silver 전극을 인쇄하여 전기적 특성을 측정하였다. Bi양이 3.28몰 첨가된 조성에서 최대의 잔류분극 (2Pr) 값을 얻었고, 이때의 값은 약 $18{\mu}C/cm^2$ 정도였다. 최적화된 조성 ($Bi_{3.28}La_{0.75}Ti_3O_{12}$)으로 BLT 타겟을 제조하여 PLD법으로 박막을 제조하였다. 박막 제조 시 압력은 $1{\times}10^{-1}\;{\sim}\;1{\times}10^{-4}\;Torr$ 범위에서 변화시켰다. $1{\times}10^{-1}\;Torr$ 압력을 제외하고는 모든 압력에서 BLT 박막이 증착되었다. 중착된 박막을 $650\;{\sim}\;800^{\circ}C$에서 30분간 열처리를 실시하고 전기적 특성을 평가한 결과, $1{\times}10^{-2}\;Torr$에서 증착한 박막에서 양호한 P-V (polarization-voltage) 이력곡선을 얻을 수 있었고, 이때의 잔류분극 (2Pr) 값은 약 $6\;{\mu}C/cm^2$ 이었다. 주사전자현미경 (SEM)을 이용하여 BLT 박막 표면의 미세구조도 관찰하였는데, 스핀코팅 법으로 증착한 경우에 관찰되었던 조대화된 입자들은 관찰되지 않았고, 상당히 양호한 입자 크기 균일도를 나타내었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.624-627
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• 2003

The BLT thin-films were one of the promising ferroelectric materials with a good leakage current and degradation behavior on Pt electrode. The BLT target was sintered at $1100^{\circ}C$ for 4 hours at the air ambient. $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin-film deposited on $Pt/Ti/SIO_2/Si$ wafer by rf magnetron sputtering method. At annealed $700^{\circ}C$, (117) and (006) peaks appeared the high intensity. The hysteresis loop of the BLT thin films showed that the remanent polarization ($2Pr=Pr^+-Pr^-$) was $16uC/cm^2$ and leakage current density was $1.8{\times}10^{-9}A/cm^2$ at 50 kV/cm with coersive electric field when BLT thin-films were annealed at $700^{\circ}C$. Also, the thin film showed fatigue property at least up to $10^{10}$ switching bipolar pulse cycles under 7 V. Therefore, we induce access to optimum fabrication condition of memory device application by rf-magnetron sputtering method in this report.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.221-225
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• 2003

The MFIS-FET(Field Effect Transistor) devices using $BLT/Y_2O_3$ buffer layer on p-Si(100) substrates were fabricated by the Sol-Gel method and conventional memory processes. The crystal structure, morphologies and electrical properties of prepared devices were investigated by using various measuring techniques. From the C-V(capacitance-voltage) data at 5V, the memory window voltage of the $Pt/BLT/Y_2O_3/si$ structure decreased from 1.4V to 0.6V with increasing the annealing temperature from $700^{\circ}C\;to\;750^{\circ}C$. The drain current (Ic) as a function of gate voltages $(V_G)$ for the $MFIS(Pt/BLT/Y_2O_3/Si(100))-FET$ devices at gate voltages $(V_G)$ of 3V, 4V and 5V, the memory window voltages increased from 0.3V to 0.8V as $V_G$ increased from 3V to 5V.