JSTS:Journal of Semiconductor Technology and Science

  • 제15권3호
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  • Pages.397-403
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  • 2015
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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SOC Test Compression Scheme Sharing Free Variables in Embedded Deterministic Test Environment

  • Wang, Weizheng (College of computer and communication Engineering, Changsha University of Science and Technology) ;
  • Cai, Shuo (College of computer and communication Engineering, Changsha University of Science and Technology) ;
  • Xiang, Lingyun (College of computer and communication Engineering, Changsha University of Science and Technology)
  • 투고 : 2015.02.01
  • 심사 : 2015.05.12
  • 발행 : 2015.06.30
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초록

This paper presents a new SOC test compression scheme in Embedded Deterministic Test (EDT) compression environment. Compressed test data is brought over the TAM from the tester to the cores in SOC and decompressed in the cores. The proposed scheme allows cores tested at the same time to share some test channels. By sharing free variables in these channels across test cubes of different cores decompressed at the same time, high encoding efficiency is achieved. Moreover, no excess control data is required in this scheme. The ability to reuse excess free variables eliminates the need for high precision in matching the number of test channels with the number of care bits for every core. Experimental results obtained for some SOC designs illustrate effectiveness of the proposed test application scheme.

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참고문헌

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