JSTS:Journal of Semiconductor Technology and Science

  • 제10권4호
  • /
  • Pages.265-275
  • /
  • 2010
  • /
  • 1598-1657(pISSN)
  • /
  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지
DOI QR코드

DOI QR Code

Rigorous Design of 22-nm Node 4-Terminal SOI FinFETs for Reliable Low Standby Power Operation with Semi-empirical Parameters

  • Cho, Seong-Jae (Electrical Engineering Department, Stanford University) ;
  • O'uchi, Shinichi (Silicon Nanoscale Device Group, Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)) ;
  • Endo, Kazuhiko (Silicon Nanoscale Device Group, Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)) ;
  • Kim, Sang-Wan (School of Electrical Engineering and Computer Science, and Inter-university Semiconductor Research Center (ISRC), Seoul National University) ;
  • Son, Young-Hwan (School of Electrical Engineering and Computer Science, and Inter-university Semiconductor Research Center (ISRC), Seoul National University) ;
  • Kang, In-Man (School of Electronics Engineering, Kyungpook National University) ;
  • Masahara, Meishoku (Silicon Nanoscale Device Group, Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)) ;
  • Harris, James S.Jr (Electrical Engineering Department, Stanford University) ;
  • Park, Byung-Gook (School of Electrical Engineering and Computer Science, Seoul National University)
  • 투고 : 2010.11.04
  • 발행 : 2010.12.31
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

키워드

참고문헌

  1. J. Chen, T. Y. Chan, I. C. Chen, P. K. Ko, C. Hu, “Subbreakdown drain leakage current in MOSFET,” IEEE Electron Device Lett., Vol.8, No.11, pp.515-517, Nov. 1987. https://doi.org/10.1109/EDL.1987.26713
  2. S. Veeraraghaven, J. G. Fossum, “Short-channel effects in SOI MOSFETs,” IEEE Trans. Electron Devices, Vol.36, No.3, pp.522-528, Mar. 1989. https://doi.org/10.1109/16.19963
  3. Y. Omura, H. Konishi, and K. Yoshimoto, “Impact of fin aspect ratio on short-channel control and drivability of multiple-gate SOI MOFET’s,” J. Semicond. Technol. Sci., Vol.8, No.4, pp.302-310, Dec. 2008. https://doi.org/10.5573/JSTS.2008.8.4.302
  4. D.-S. Woo, J.-H. Lee, W. Y. Choi, B.-Y. Choi, Y.-J. Choi, J. D. Lee, and B.-G. Park, “Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile,” IEEE Trans. Nanotechnol., Vol.1, No.4, pp.233-237, Dec. 2002. https://doi.org/10.1109/TNANO.2002.807373
  5. D.-S. Woo, B. Y. Choi, W. Y. Choi, M. W. Lee, J. D. Lee, and B.-G. Park, “30 nm self-aligned FinFET with large source/drain fan-out structure,” Electron. Lett., Vol.39, No.15, pp.1154-1155, Jul. 2003. https://doi.org/10.1049/el:20030656
  6. ATHENA/ATLAS User’s Manual, Silvaco International, Nov/Dec. 2008.
  7. K. Endo, S. O’uchi, Y. Ishikawa, Y. Liu, T. Matsukawa, K. Sakamoto, J. Tsukada, K. Ishii, H. Yamauchi, E. Suzuki, and M. Masahara, “Enhancing SRAM cell performance by using independent double-gate FinFET,” in IEDM Tech. Dig., 2008, pp.857-860.
  8. T.-S. Park, H. J. Cho, J. D. Choe, S. Y. Han, D. Park, K. Kim, E. Yoon, and J.-H. Lee, “Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (Bulk FinFETs),” IEEE Trans. Electron Devices, Vol.53, No.3, pp. 481-487, Mar. 2006. https://doi.org/10.1109/TED.2005.864392
  9. H. Yamauchi, “A scaling trend of variation-tolerant SRAM circuit design in deeper nanometer era,” J. Semicond. Technol. Sci., Vol.9, No.1, pp.37-50, Mar. 2009. https://doi.org/10.5573/JSTS.2009.9.1.037
  10. K. Endo, S. O’uchi, Y. Ishikawa, Y. Liu, T. Matsukawa, K. Sakamoto, M. Masahara, J. Tsukada, K. Ishii, H. Yamauchi, and E. Suzuki, “Independent-double-gate FinFET SRAM for leakage current reduction,” IEEE Electron Device Lett., Vol.30, No.7, pp.757-759, Jul. 2009. https://doi.org/10.1109/LED.2009.2021075
  11. S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley-Interscience, New York, USA, 2007, pp.96-98.
  12. R. F. Pierret, Semiconductor Device Fundamentals, Addison Wesley, Massachusetts, USA, 1996, p. 116.
  13. E. O. Kane, “Theory of tunneling,” J. Appl. Phys., Vol.32, No.1, pp.83-91, Jan. 1961. https://doi.org/10.1063/1.1735965
  14. G. A. M. Hurkx, D. B. M. Klaassen, and M. P. G. Knuvers, “A new recombination model for device simulation including tunneling,” IEEE Trans. Electron Devices, Vol.39, No.2, pp.331-338, Feb. 1992. https://doi.org/10.1109/16.121690
  15. A. Schenk, “Rigorous theory and simplified model of the band-to-band tunneling in silicon,” Solid State Electron., Vol.36, No.1, pp.19-34, Jan. 1993. https://doi.org/10.1016/0038-1101(93)90065-X
  16. J.-H. Chen, S.-C. Wong, and Y.-H. Wang, “An analytical three-terminal band-to-band tunneling model on GIDL in MOSFET,” IEEE Trans. Electron Devices, Vol.48, No.7, pp.1400-1405, Jul. 2001. https://doi.org/10.1109/16.930658
  17. T. Y. Chan, J. Chen, P. K. Ko, and C. Hu, “The impact of gate-drain leakage current on MOSFET Scaling,” in IEDM Tech. Dig., 1987, pp.718-721.
  18. S. K. Sung, Y. J. Choi, J. D. Lee, and B.-G. Park, “Fabrication of ultra-thin line using sidewall structure and the application for nMOSFET,” The 6th Korean Conf. Semicond., pp.617-618, Feb. 1999.
  19. Y.-K. Choi, T.-J. King, and C. Hu, “A spacer patterning technology for nanoscale CMOS,” IEEE Trans. Electron Devices, Vol.49, No.3, pp.436-441, Mar. 2002. https://doi.org/10.1109/16.987114
  20. B.-G. Park, D. H. Kim, K. R. Kim, K.-W. Song, and J. D. Lee, “Single-electron transistors fabricated with sidewall spacer patterning,” Superlattices Microstruct., Vol.34, No.3-6, pp.231-239, Sep.-Dec. 2003. https://doi.org/10.1016/j.spmi.2004.03.013
  21. D. M. Caughey and R. E. Thomas, “Carrier mobilities in silicon empirically related to doping and field.” Proc. IEEE, Vol.55, No.12, pp.2192-2193, Dec. 1967. https://doi.org/10.1109/PROC.1967.6123
  22. S. Selberherr, “Process and device modeling for VLSI”, Microelectron. Reliab., Vol.24, No.2, pp. 225-257, Mar.-Apr. 1984. https://doi.org/10.1016/0026-2714(84)90450-5
  23. W. Shockley and W. T. Read, “Statistics of the recombination of holes and electrons”, Phys. Rev. Vol.87, No.5, pp.835-842, Sep. 1952. https://doi.org/10.1103/PhysRev.87.835
  24. R. N. Hall, “Electron hole recombination in germanium”, Phys. Rev. Vol.87, No.2, p.387, Jul. 1952.
  25. J. W. Slotboom and H. C. De Graaf, “Measurements of bandgap narrowing in silicon bipolar transistors”, Solid State Electron., Vol.19, No.10, pp.857-862, Oct. 1976. https://doi.org/10.1016/0038-1101(76)90043-5
  26. G. A. M. Hurkx, D. B. M. Klaassen, M. P. G. Knuvers, and F. G. O’Hara, “A new recombination model describing heavy-doping effects and low temperature behaviour”, in IEDM Tech. Dig., 1989, pp.307-310.
  27. Y. Apanovich, P. Blakey, R. Cottle, E. Lyumkis, B. Polsky, A. Shur, and A. Tcherniaev, “Numerical simulation of submicrometer devices including coupled nonlocal transport and nonisothermal effects,” IEEE Trans. Electron Devices, Vol.42, No.2, pp.890-898, May 1995. https://doi.org/10.1109/16.381985
  28. Process Integration, Devices, and Structures (PIDS), International Technology Roadmap for Semiconductors (ITRS), 2009 edition, p.9.
  29. K. Tanaka, K. Takeuchi, M. Hane, “Practical FinFET design considering GIDL for LSTP (low standby power) devices,” in IEDM Tech. Dig., 2005, pp.1001-1004.
  30. F. Gilibert, D. Rideau, A. Dray, F. Agut, M. Minondo, A. Juge, P. Masson, and R. Bouchakour, “Characterization and modeling of gate-induceddrain- leakage,” IEICE Trans. Electron., Vol.E88-C, No.5, pp.829-837, May 2005. https://doi.org/10.1093/ietele/e88-c.5.829
  31. S. Cho, J. H. Lee, S. O’uchi, K. Endo, M. Masahara, and B.-G. Park, “Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL),” Solid-State Electron., Vol.54, No.10, pp.1060-1065, Oct. 2010. https://doi.org/10.1016/j.sse.2010.05.013

피인용 문헌

  1. Analyses on Small-Signal Parameters and Radio-Frequency Modeling of Gate-All-Around Tunneling Field-Effect Transistors vol.58, pp.12, 2011, https://doi.org/10.1109/TED.2011.2167335
  2. Analytical Models for Three-Dimensional Ion Implantation Profiles in FinFETs vol.32, pp.12, 2013, https://doi.org/10.1109/TCAD.2013.2277975
  3. Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications vol.60, pp.1, 2013, https://doi.org/10.1109/TED.2012.2225063
  4. Insights into operation of planar tri-gate tunnel field effect transistor for dynamic memory application vol.122, pp.4, 2017, https://doi.org/10.1063/1.4996094
  5. Retention and Scalability Perspective of Sub-100-nm Double Gate Tunnel FET DRAM vol.64, pp.4, 2017, https://doi.org/10.1109/TED.2017.2662703