JSTS:Journal of Semiconductor Technology and Science

  • 제8권1호
  • /
  • Pages.11-20
  • /
  • 2008
  • /
  • 1598-1657(pISSN)
  • /
  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지
DOI QR코드

DOI QR Code

Two-Bit/Cell NFGM Devices for High-Density NOR Flash Memory

  • Lee, Jong-Ho (School of Electrical Engineering and Computer Science, Kyungpook National University)
  • 발행 : 2008.03.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

키워드

참고문헌

  1. International Technology Roadmap for Semiconductor (ITRS; Semiconductor Industry Association, San Jose, 2006)
  2. Byung Yong Choi, Byung-Gook Park, Yong Kyu Lee, Suk Kang Sung, Tae Yong Kim, Eun Suk Cho, Hye Jin Cho, Chang Woo Oh, Sung Hwan Kim, Dong Won Kim, Choong-Ho Lee, and Donggun Park, 'Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascene gate process,' Symp. VLSI Tech. Dig., pp. 118-119, 2005
  3. Yong Kyu Lee, Jae Sung Shim, Suk Kang Sung, Chang Ju Lee, Tae Hun Kim, Jong Duk Lee, Byung Gook Park, Dong Hun Lee, and Young Wug Kim, 'Multilevel Vertical-Channel SONOS Nonvolatile Memory on SOI,' IEEE Electron Device Lett., vol. 23, no. 11, pp. 664-666, 2002 https://doi.org/10.1109/LED.2002.805001
  4. Masatoshi Fukuda, Toshiro Nakanishi, and Yasuo Nara, 'Scaled 2-bit/cell SONOS type nonvolatile memory technology for sub-90nm embedded application using SiN sidewall trapping structure,' IEDM Tech. Dig., pp. 909-912, 2003
  5. Yong Kyu Lee, Ki Hwan Song, Jae Woong Hyun, Jong Duk Lee, Byung Gook Park, Sung Taeg Kang, Jeong Dong Choe, Sang Yeon Han, Jeong Nam Han, Sung Woo Lee, O. Ik Kwon, Chilhee Chung, Donggun Park, and Kinam Kim, 'Twin SONOS memory with 30-nm storage nodes under a merged gate fabricated with inverted sidewall and damascene process,' IEEE Electron Device Lett., vol. 25, no. 5, pp. 317-319, 2004 https://doi.org/10.1109/LED.2004.826535
  6. Tsz Yin Man and Mansun Chan, 'A 2-bit highly scalable nonvolatile memory cell with two electrically isolated charge trapping sites,' Microelectronics Reliability, vol. 45, pp. 349-354, 2005 https://doi.org/10.1016/j.microrel.2004.08.016
  7. Boaz Eitan, Paolo Pavan, Ilan Bloom, Efraim Aloni, Aviv Frommer, and David Finzi, 'NROM: a novel localized trapping, 2-bit nonvolatile memory cell,' IEEE Electron Device Lett., vol. 21, no. 11, pp. 543-545, 2000 https://doi.org/10.1109/55.877205
  8. H. Tomiye, T. Terano, K. Nomoto, and T. Kobayashi, 'Novel 2-bit/cell metal?oxide?nitride?oxide?semiconductor memory device with wrapped-control-gate structure that achieves source-side hot-electron injection,' Jpn. J. Appl. Phys., vol. 44, pp. 4825-4830, 2005 https://doi.org/10.1143/JJAP.44.4825
  9. C.C. Yeh, W.J. Tsai, M.I. Liu, T.C. Lu, S.K. Cho, C.J. Lin, Tahui Wang, Sam Pan, and Chih-Yuan Lu, 'PHINES: a novel low power program/erase, small pitch, 2-bit per cell flash memory,' IEDM Tech. Dig., pp. 931-934, 2002
  10. M. J. Kriton and M. J. Uren, 'Noise in solid state microstructure: a new perspective on individual defects, interface states, and low-frequency (1/f) noise,' Adv. in Phys., vol. 38, no. 4, p. 367, 1989 https://doi.org/10.1080/00018738900101122
  11. M. H. Tsai and T.-P. Ma, 'The impact of device scaling on the current fluctuations in MOSFET's,' IEEE Trans. on Electron Devices, vol. 41, no. 11, pp. 2061-2068, 1994 https://doi.org/10.1109/16.333823
  12. N. Tega, H. Miki, T. Osabe, A. Kotabe, K. Otsuga, H. Kurata, S. Kamohara, K. Tokami, Y. Ikeda, and R. Yamada, 'anomalously large threshold voltage fluctuation by complex random telegraph signal in floating gate memory,' IEDM Tech. Dig., pp.1-4, 2006
  13. L. Perniola B. De Salvo, G. Ghibaudo, A. Foglio Para, G. Pananakakis, T. Baron, S. Lombarodo, L. Baldi, 'A theoretical study of the influence of technological parameter fluctuations on the electrical characteristics of multi nanocrystal memories,' Proc. Si Nanoelectronics Workshop, pp. 56-57, 2003
  14. A. Thean and J.-P. Leburton, 'Flash memory:towards single-electronics,' IEEE Potentials, pp. 35-41, Oct. /Nov. 2002
  15. ATLAS Device Simulation Software (Silvaco International, Santa Clara, CA, 2006) Ver. 5.11.3.C
  16. G. L. Chindalore, C. T. Swift, and D. Burnett, 'A new combination-erase technique for erasing nitride based (SONOS) nonvolatile memories,' IEEE Electron Device Lett., vol. 24, pp. 257-259, 2003 https://doi.org/10.1109/LED.2003.810883
  17. B. Kim, C.-K. Baek, W. Kwon, Y.-H. Jeong, and D. M. Kim, 'Simple experimental determination of the spread of trapped hot holes injected in Silicon-Oxide-Nitride-Oxide-Silicon(SONOS) cells: optimized erase and cell shrinkage,' Jpn. J. Appl. Phys., vol.43, pp. L1611-L1613, 2004 https://doi.org/10.1143/JJAP.43.L1611
  18. P. B. Kumar, E. Murakami, S. Kamohara, and S. Mahapatra, 'Endurance and retention characteristics of SONOS EEPROMs operated using BTBT induced hot hole erase,' in Proc. IRPS, pp. 699-700, 2006
  19. E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, 'Characterization of channel hot electron injection by the subthreshold slope of $NROM^TM$ device', IEEE Electron Dev. Lett., vol. 22, pp. 556-558, 2001 https://doi.org/10.1109/55.962662

피인용 문헌

  1. Independent Double-Gate Fin SONOS Flash Memory Fabricated With Sidewall Spacer Patterning vol.56, pp.8, 2009, https://doi.org/10.1109/TED.2009.2024228
  2. A 2-Bit Recessed Channel Nonvolatile Memory Device With a Lifted Charge-Trapping Node vol.8, pp.1, 2009, https://doi.org/10.1109/TNANO.2008.2006049
  3. A Gated Twin-Bit (GTB) Nonvolatile Memory Device and Its Fabrication Method vol.8, pp.5, 2009, https://doi.org/10.1109/TNANO.2009.2019641
  4. A Vertical 4-Bit SONOS Flash Memory and a Unique 3-D Vertical nor Array Structure vol.9, pp.1, 2010, https://doi.org/10.1109/TNANO.2009.2026173
  5. A Compact Model for Channel Coupling in Sub-30 nm NAND Flash Memory Device vol.50, pp.10, 2011, https://doi.org/10.1143/JJAP.50.100204
  6. Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption vol.50, pp.4, 2011, https://doi.org/10.1143/JJAP.50.04DD03
  7. DIBL-Induced Program Disturb Characteristics in 32-nm NAND Flash Memory Array vol.58, pp.10, 2011, https://doi.org/10.1109/TED.2011.2161313
  8. LAyer Selection by ERase (LASER) With an Etch-Through-Spacer Technique in a Bit-Line Stacked 3-D nand Flash Memory Array vol.58, pp.7, 2011, https://doi.org/10.1109/TED.2011.2142417
  9. Stacked Gated Twin-Bit (SGTB) SONOS Memory Device for High-Density Flash Memory vol.11, pp.2, 2012, https://doi.org/10.1109/TNANO.2011.2172217
  10. The Compact Modeling of Channel Potential in Sub-30-nm NAND Flash Cell String vol.33, pp.3, 2012, https://doi.org/10.1109/LED.2011.2179283
  11. Gated twin-bit silicon–oxide–nitride–oxide–silicon NAND flash memory for high-density nonvolatile memory vol.54, pp.6, 2015, https://doi.org/10.7567/JJAP.54.064201
  12. Extended Word-Line NAND Flash Memory vol.48, pp.8, 2009, https://doi.org/10.1143/JJAP.48.081203