Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Efficient Operator Design Using Variable Groups

변수그룹을 이용한 효율적인 연산기 설계

  • Kim, Yong-Eun (Div. of Electronic & Information Engineering Chonbuk University) ;
  • Chung, Jin-Gyun (Div. of Electronic & Information Engineering Chonbuk University)
  • 김용은 (전북대학교 전자정보공학부) ;
  • 정진균 (전북대학교 전자정보공학부)
  • Published : 2008.01.25
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Abstract

In this paper, we propose a partial product addition method using variable groups in the design of operators such as multipliers and digital filters. By this method, full adders can be replaced with simple logic circuits. To show the efficiency of the proposed method, we applied the method to the design of squarers and precomputer blocks of FIR filters. In case of 7 bit and 8 bit squarers, it is shown that by the proposed method, area, power and delay time can be reduced up to {22.1%, 20.1%, 14%} and {24.7%, 24.4%, 6.7%}, respectively, compared with the conventional method. The proposed FIR precomputer circuit leads to up to {63.6%, 34.4%, 9.8%} reduction in area, power consumption and propagation delay compared with previous method.

본 논문에서는 곱셈기나 필터 등에서 연산을 위해 부분곱을 더할 때 더해질 변수를 그룹화하여 연산기를 설계하는 방법을 제시한다. 제안한 그룹화 알고리즘을 사용하면 기존의 full adder cell이 간단한 로직회로로 대치되고 이에 따라 면적, 전력소모, 속도면에서 효율적인 디자인이 가능하다. 제안한 방법을 7bit, 8bit 제곱기 및 FIR 필터에 사용되는 precomputer 블록에 적용한 결과 기존의 방법 보다 면적, 전력소모, 속도에서 각각 {22.1%, 20.1%, 14%}, {24.7%, 24.4%, 6.7%}, {63.6%, 34.4%, 9.8%} 의 이득 있음을 보인다.

Keywords

References

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