A 0.8V 816nW Delta-Sigma Modulator Applicaiton for Cardiac Pacemaker

카디악 페이스메이커용 0.8V 816nW 델타-시그마 모듈레이터

  • Lee, Hyun-Tae (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.) ;
  • Heo, Dong-Hun (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.) ;
  • Roh, Jeong-Jin (Dep. of Electrical Engineering and Computer Science, Hanyang Univ.)
  • 이현태 (한양대학교 전자전기제어계측공학과) ;
  • 허동훈 (한양대학교 전자전기제어계측공학과) ;
  • 노정진 (한양대학교 전자컴퓨터공학부)
  • Published : 2008.01.25

Abstract

This paper discusses theimplementation of the low-voltage, low-power, third-order, 1-bit switched capacitor delta-sigma modulator of the implantable cardiac pacemaker. The distributed, feed-forward structure and bulk-driven OTA were used in order to achieve an efficient operation under a supply voltage of 1V or lower. The designed modulator has a dynamic range of 49dB at 0.9V supply voltage and consumes 816nW of power. Such a significant reduction in power consumption allows diverse applications, not only in pacemakers, but also in implantable biomedical devices that operate with limited battery power. The core chip size of the modulator is $1000{\mu}m*500{\mu}m$ manufactured, with the $0.18{\mu}m$ CMOS standard process.

이번 논문은 implantable cardiac 페이스메이커의 검출 단 로서 저전압, 저전력 단일-비트 삼차 델타-시그마 모듈레이터를 구현하였다. 1V이하의 전원 전압에서 효과적으로 동작하기 위하여 distributed feedforward구조와 벌크-드리븐 OTA를 활용하였다. 설계된 모듈레이터는 0.8V의 전원 전압에서 49dB의 dynamic range를 가지면서 816nW의 파워를 소모하였다. 파워 소모를 획기적으로 줄임으로서 페이스메이커뿐만 아니라 제한된 배터리에서 동작하는 implantable 의료 기기에서 다양한 활용이 가능할 것으로 생각된다. 본 모듈레이터의 칩 크기는 $1000{\mu}m{\times}500{\mu}m$로서 $0.18{\mu}m$ CMOS standard 공정으로 제작되었다.

Keywords

References

  1. L. S. Y. Wong, S. Hossain, A. Ta, J. Edvinsson, D. H. Rivas and H. Naas, 'A Very Low-Power CMOS Mixed-Signal IC for Implantable Pacemaker Application,' IEEE J. Solid-State Circuits, vol.39, pp. 2446-2456, Dec. 2004 https://doi.org/10.1109/JSSC.2004.837027
  2. A. Gerosa, A. Novo and A. Neviani 'An Analog Front End for the Acquisition of Biomedical Signals Fully Integrated in a 0.8$\mu$m CMOS Process,' in Southwest Symp. Mixed-Signal Design, Feb. 2001, pp. 152-157
  3. J. Neves Rodrigues, V. Owall and L. Sornmo, 'QRS Detection for Pacemakers in a Noisy Environment Using a Time Lagged Artificial Neural Network.' in Proc. IEEE Int. Symp. Circuits and Syst., vol. 3, 2001, pp. 596-599
  4. A. Gerosa and A. Neviani 'A 1.8$\mu$W Sigma-Delta modulator for 8-Bit Digitization of Cardiac Signal in Implantable Pacemakers Operating Down to 1.8V,' IEEE trans. Circuits and Syst., II, vol. 52, pp. 71-76, Feb. 2005
  5. S. S. Rajput and S. S. Jamuar, 'Low Voltage Analog Circuit Techniques,' in IEEE Circuits and Syst. Mag., vol. 2, First quarter 2002, pp. 24-42
  6. A. L. Coban and P. E. Allen, 'A New Fourth-Order Single-Loop Delta-Sigma Modulator for Audio Applications,' in Proc. IEEE Int. Symp. Circuits and Syst., vol. 1, May 1996, pp. 461-464
  7. R. Schreier, Understanding Delta-Sigma Data Converters. New York : WILEY/IEEE Press, 2004
  8. L. Yao, M. Steyaert and W. Sansen, 'A 1-V, 1-MS/s, 88-dB Sigma-Delta Modulator in 0.13$\mu$m Digital CMOS Technology,' in Proc. Symp. VLSI Circuits Dig. Tech. Papers, June 2005, pp. 180-183
  9. B. J. Blalock, P. E. Allen, G. A. Rincon-Mora, ' Designing 1-V Op Amps Using Standard Digital CMOS Technology,' IEEE Trans. Circuits and Syst. II, vol. 45, pp. 769-780, July 1998
  10. Y. Haga and H. Zare-Hoseini, 'Design of a 0.8 Volt Fully Differential CMOS OTA Using the Bulk-Driven Technique,' in Proc. IEEE Int. Symp. Circuits and Syst., vol. 1, May 2005, pp. 220-223
  11. J. Adut, J. Silva-Martinez and M. Rocha-Perez, 'A 10.7MHz Sixth-order SC Ladder Filter in 0.35$\mu$m CMOS Technology,' IEEE Trans. Circuits and Syst., vol. 53, Aug. 2006, pp. 1625-1635 https://doi.org/10.1109/TCSI.2006.879070
  12. R. Jacob Baker, CMOS Circuit Design, Layout, and simulation: IEEE Press, 2005
  13. T. B. Cho and P. R. Gray, 'A 10 b, 20Msample/s, 35mW Pipeline A/D Converter,' IEEE J. Solid-Stage Circuits, vol. 30, pp. 166-172, March 1995 https://doi.org/10.1109/4.364429
  14. V. S. L. Cheung and H. C. Luong, 'A 0.9V 0.5$\mu$W CMOS Single-Switched Op-Amp Signal- Conditioning System for Pacemaker Applications,' in Proc. IEEE Int. Solid-State Circuits conf. Dig. Tech. Papers, vol. 1, 2003, pp. 408-503
  15. A. Gerosa and A. Neviani 'A Very Low-Power 8-bit Sigma-Delta Converter in a 0.8$\mu$m CMOS Technology of the Sensing Chain of a Cardiac Pacemaker,' in Proc. IEEE Int. Symp. Circuits and Syst., vol. 5, May 2003, pp. 49-52