References
- L. S. Y. Wong, S. Hossain, A. Ta, J. Edvinsson, D. H. Rivas and H. Naas, 'A Very Low-Power CMOS Mixed-Signal IC for Implantable Pacemaker Application,' IEEE J. Solid-State Circuits, vol.39, pp. 2446-2456, Dec. 2004 https://doi.org/10.1109/JSSC.2004.837027
-
A. Gerosa, A. Novo and A. Neviani 'An Analog Front End for the Acquisition of Biomedical Signals Fully Integrated in a 0.8
$\mu$ m CMOS Process,' in Southwest Symp. Mixed-Signal Design, Feb. 2001, pp. 152-157 - J. Neves Rodrigues, V. Owall and L. Sornmo, 'QRS Detection for Pacemakers in a Noisy Environment Using a Time Lagged Artificial Neural Network.' in Proc. IEEE Int. Symp. Circuits and Syst., vol. 3, 2001, pp. 596-599
-
A. Gerosa and A. Neviani 'A 1.8
$\mu$ W Sigma-Delta modulator for 8-Bit Digitization of Cardiac Signal in Implantable Pacemakers Operating Down to 1.8V,' IEEE trans. Circuits and Syst., II, vol. 52, pp. 71-76, Feb. 2005 - S. S. Rajput and S. S. Jamuar, 'Low Voltage Analog Circuit Techniques,' in IEEE Circuits and Syst. Mag., vol. 2, First quarter 2002, pp. 24-42
- A. L. Coban and P. E. Allen, 'A New Fourth-Order Single-Loop Delta-Sigma Modulator for Audio Applications,' in Proc. IEEE Int. Symp. Circuits and Syst., vol. 1, May 1996, pp. 461-464
- R. Schreier, Understanding Delta-Sigma Data Converters. New York : WILEY/IEEE Press, 2004
-
L. Yao, M. Steyaert and W. Sansen, 'A 1-V, 1-MS/s, 88-dB Sigma-Delta Modulator in 0.13
$\mu$ m Digital CMOS Technology,' in Proc. Symp. VLSI Circuits Dig. Tech. Papers, June 2005, pp. 180-183 - B. J. Blalock, P. E. Allen, G. A. Rincon-Mora, ' Designing 1-V Op Amps Using Standard Digital CMOS Technology,' IEEE Trans. Circuits and Syst. II, vol. 45, pp. 769-780, July 1998
- Y. Haga and H. Zare-Hoseini, 'Design of a 0.8 Volt Fully Differential CMOS OTA Using the Bulk-Driven Technique,' in Proc. IEEE Int. Symp. Circuits and Syst., vol. 1, May 2005, pp. 220-223
-
J. Adut, J. Silva-Martinez and M. Rocha-Perez, 'A 10.7MHz Sixth-order SC Ladder Filter in 0.35
$\mu$ m CMOS Technology,' IEEE Trans. Circuits and Syst., vol. 53, Aug. 2006, pp. 1625-1635 https://doi.org/10.1109/TCSI.2006.879070 - R. Jacob Baker, CMOS Circuit Design, Layout, and simulation: IEEE Press, 2005
- T. B. Cho and P. R. Gray, 'A 10 b, 20Msample/s, 35mW Pipeline A/D Converter,' IEEE J. Solid-Stage Circuits, vol. 30, pp. 166-172, March 1995 https://doi.org/10.1109/4.364429
-
V. S. L. Cheung and H. C. Luong, 'A 0.9V 0.5
$\mu$ W CMOS Single-Switched Op-Amp Signal- Conditioning System for Pacemaker Applications,' in Proc. IEEE Int. Solid-State Circuits conf. Dig. Tech. Papers, vol. 1, 2003, pp. 408-503 -
A. Gerosa and A. Neviani 'A Very Low-Power 8-bit Sigma-Delta Converter in a 0.8
$\mu$ m CMOS Technology of the Sensing Chain of a Cardiac Pacemaker,' in Proc. IEEE Int. Symp. Circuits and Syst., vol. 5, May 2003, pp. 49-52