Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Low Power ECC H-matrix Optimization Method using an Ant Colony Optimization

ACO를 이용한 저전력 ECC H-매트릭스 최적화 방안

  • Lee, Dae-Yeal (Department of Electrical Electronic Engineering, Yonsei University) ;
  • Yang, Myung-Hoon (Department of Electrical Electronic Engineering, Yonsei University) ;
  • Kim, Yong-Joon (Department of Electrical Electronic Engineering, Yonsei University) ;
  • Park, Young-Kyu (Department of Electrical Electronic Engineering, Yonsei University) ;
  • Yoon, Hyun-Jun (Department of Electrical Electronic Engineering, Yonsei University) ;
  • Kang, Sung-Ho (Department of Electrical Electronic Engineering, Yonsei University)
  • 이대열 (연세대학교 전기전자공학과) ;
  • 양명훈 (연세대학교 전기전자공학과) ;
  • 김용준 (연세대학교 전기전자공학과) ;
  • 박영규 (연세대학교 전기전자공학과) ;
  • 윤현준 (연세대학교 전기전자공학과) ;
  • 강성호 (연세대학교 전기전자공학과)
  • Published : 2008.01.25
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Abstract

In this paper, a method using the Ant Colony Optimization(ACO) is proposed for reducing the power consumption of memory ECC checker circuitry which provide Single-Error Correcting and Double-Error Detecting(SEC-DED). The H-matrix which is used to generate SEC-DED codes is optimized to provide the minimum switching activity with little to no impact on area or delay using the symmetric property and degrees of freedom in constructing H-matrix of Hsiao codes. Experiments demonstrate that the proposed method can provide further reduction of power consumption compared with the previous works.

본 논문에서는 Ant Colony Optimization(ACO)을 이용하여 Single-Error Correcting & Double-Error Detecting(SEC-DED)을 제공하는 메모리 ECC 체커 회로의 소비전력을 절감하는 방안을 제시한다. H-매트릭스를 통해 구현되는 SEC-DED 코드인 Hsiao 코드의 대칭성과 H-매트릭스 구성상의 높은 자유도를 이용하여 회로의 면적, 딜레이에 영향을 주지 않고 최소의 비트 트랜지션이 일어나도록 H-매트릭스를 최적화한다. 실험을 통하여 H-매트릭스의 최적화를 위한 ACO 매핑과 파라메터의 설정을 알아보고 이의 구현 결과를 랜덤 매트릭스 구성을 통한 방식 및 기존의 GA알고리즘을 이용한 최적화 방식과 비교하여 소비 전력이 기존의 방식에 비해 절감될 수 있음을 보여준다.

Keywords

References

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