Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Memory BIST Circuit Generator System Design Based on Fault Model

고장 모델 기반 메모리 BIST 회로 생성 시스템 설계

  • Lee Jeong-Min (Department of Computing, Soongsil University) ;
  • Shim Eun-Sung (Department of Computing, Soongsil University) ;
  • Chang Hoon (Department of Computing, Soongsil University)
  • 이정민 (숭실대학교 컴퓨터학과) ;
  • 심은성 (숭실대학교 컴퓨터학과) ;
  • 장훈 (숭실대학교 컴퓨터학과)
  • Published : 2005.02.01
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Abstract

In this paper, we propose a memory BIST Circuit Creation System which creates BIST circuit based on user defined fault model and generates the optimized march test algorithm. Traditional tools have some limit that regenerates BIST circuit after changing the memory type or test algorithm. However, this proposed creation system can automatically generate memory BIST circuit which is suitable in the various memory type and apply algorithm which is required by user. And it gets more efficient through optimizing algorithms for fault models which is selected randomly according to proposed nile. In addition, it support various address width and data and consider interface of IEEE 1149.1 circuit.

본 논문에서는 사용자로부터 테스트하고자 하는 고장 모델을 입력받아 적절한 much 테스트 알고리즘을 만들고 BIST 회로를 생성해 주는 Memory BIST Circuit Creation System(MBCCS) 을 제안하고 있다. 기존의 툴들은 널리 사용되고 있는 알고리즘에 국한되어 메모리의 사양이 변할 경우 거기에 맞는 BIST 회로를 다시 생성해주는 번거로움이 있었다. 하지만 본 논문에서 제안한 툴에서는 다양해진 메모리 구조에 적합한 메모리 BIST 회로를 사용자 요구에 맞는 알고리즘을 적용해서 자동적으로 생성하게 하였고, 임의적으로 선택된 고장 모델에 대한 알고리즘을 제안된 규칙에 따라 최적화함으로 해서 효율성을 높였다. 또한 다양한 크기의 폭을 갖는 주소와 데이터를 지원하며 IEEE 1149.1 회로와의 인터페이스도 고려하였다.

Keywords

References

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