Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of a Low-Power CVSL Full Adder Using Low-Swing Technique

Low-Swing 기술을 이용한 저 전력 CVSL 전가산기 설계

  • Kang Jang Hee (Department of Electronics Engineering Kangwon National University) ;
  • Kim Jeong Beom (Department of Electrical and Computer Engineering Kangwon National University)
  • 강장희 (강원대학교 전자공학과) ;
  • 김정범 (강원대학교 전기전자정보통신공학부)
  • Published : 2005.02.01
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Abstract

In this paper, we propose a new Low-Swing CVSL full adder for low power consumption. An $8\times8$ parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing the previous works, this circuit is reduced the power consumption rate of $13.1\%$ and the power-delay-product of $14.3\%$. The validity and effectiveness of the proposes circuits are verified through the HSPICE under Hynix $0.35{\mu}m$ standard CMOS process.

본 논문은 기존의 CVSL 전가산기 회로 내부에 Low-Swing 기술의 특성을 갖도록 NMOS 트랜지스터를 추가하여 감소된 출력전압으로 동작하는 CVSL 전가산기를 제안하였다. 또한 제안한 Low-Swing CVSL 전가산기를 이용하여 $8\times8$ 병렬 곱셈기를 구성한 후 회로의 성능을 평가하였다. 본 논문에서 제안한 Low-Swing CVSL 전가산기 회로는 $13.1\%$의 전력감소와 $14.3\%$의 전력소모와 지연시간의 곱(power-delay-product) 감소가 이루어졌다 Hynix $0.35{\mu}m$ 표준 CMOS 공정을 사용하여 HSPICE로 시뮬레이션하고 그 동작 특성을 검증하였다.

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References

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