The Development on Embedded Memory BIST IP Automatic Generation System for the Dual-Port of SRAM

SRAM 이중-포트를 위한 내장된 메모리 BIST IP 자동생성 시스템 개발

  • 심은성 (숭실대학교 컴퓨터학과) ;
  • 이정민 (숭실대학교 컴퓨터학과) ;
  • 이찬영 (숭실대학교 컴퓨터학과) ;
  • 장훈 (숭실대학교 컴퓨터학과)
  • Published : 2005.02.01

Abstract

In this paper, we develop the common CAD tool that creates the automatically BIST IP by user settings for the convenient test of embedded memory. Previous tools have defect that when memory model is changed, BIST IP must re-designed depending on memory model because existing tools is limited the widely used algorithms. We develop the tool that is created automatic BIST IP. It applies the algorithm according to the memory model which user requests We usually use the multi-port asynchronous SRAM needless to refresh as the embedded memory. However, This work researches on the dual-port SRAM.

본 논문에서는 내장된 메모리의 테스트를 편리하게 하기 위하여 간단한 사용자 설정에 의해 자동으로 BIST IP를 생성해 내는 범용 CAD 툴을 개발하였다. 기존의 툴들은 널리 사용되고 있는 알고리즘에 국한되어 있어 메모리의 모델이 변하게 되면 다시 메모리 모델에 따라 BIST IP를 설계해야 하는 번거로움이 있었다. 하지만 본 논문에서는 사용자가 원하는 메모리 모델에 따라 알고리즘을 적용해 자동으로 BIST IP를 생성해 주는 툴을 개발하였다. 내장된 메모리로는 리프레쉬가 필요 없는 다중-포트 비동기식 SRAM이 가장 많이 사용되며, 본 연구에서는 이중-포트 SRAM에 대하여 연구 하였다.

Keywords

References

  1. Benso, A., Di Carlo, S., Di Natale, G., Prinetto, P., Lobetti Bodoni, M., 'A programmable BIST architecture for clusters of multiple-port SRAMs,' International Test Conference, pp. 557-566, 2000 https://doi.org/10.1109/TEST.2000.894249
  2. A. Bommireddy, J. Khare, S. Shaikh, S. Su. 'Test and debug of networking SoCs a case study,' Montreal, pp. 121-126, 2000 https://doi.org/10.1109/VTEST.2000.843835
  3. IEEE Stndard 1149.1-1990, 'IEEE Standards Test Access Port and boundary-scan Architecture,' IEEE Standards Board, New York, 1990
  4. Test Technology Standards Committee, 'IEEE Standard Test Access Port and Boundary-Scan Architecture,' IEEE Computer Society Press, 1993
  5. Parulkar, I., Ziaja, T., Pendurkar, R., D'Souza, A. and Majumdar, A., 'A scalable, low cost design-for-test architecture for UltraSPARC/spl trade/ chip multi processors,' International Test Conference. pp. 726-735, 2002 https://doi.org/10.1109/TEST.2002.1041825
  6. Braden, J., Lin, Q. and Smith, B., 'Use of BIST in Sun FireTM servers,' In Proc. International Test Conference. pp. 1017-1022, 2001
  7. R. Raina, R. Bailey, D. Belete, V. Khosa, R. Molyneaux, J. Prado, A. Razdan, 'DFT Advances in Motorola's Next-Generation 74xx PowerPCTM Microprocessor,' International Test Conference, pp. 131-140, 2000 https://doi.org/10.1109/TEST.2000.894200
  8. Daehan Youn, Ohyoung Song, Hoon Chang, 'Design-for-testability of the FLOVA,' In Proceedings of the Second IEEE Asia Pacific Conference, pp. 28-30, 2000
  9. Appello, D., Fudoli, A., Tancorre, V., Corno, F., Rebaudengo, M., Sonza Reorda, M., 'A BIST-based solution for the diagnosis of embedded memories adopting image processing techniques,' In Proceedings On-Line Testing Workshop, pp. 206-210, 2002 https://doi.org/10.1109/OLT.2002.1030220
  10. Memory BistCoreTM User's Reference Manual, GeneSys TestWare, Revision 14, June, 1998
  11. Yuejian Wu and Sanjay Gupta, 'Built-In Self-Test for Multi-Port RAMs', IInternational Test Conference, 1997 https://doi.org/10.1109/ATS.1997.643989
  12. Hamdioui, S., Rodgers, M., A. J. van de Goor, Eastwick, D., 'March tests for realistic faults in two-port memories,' Memory Technology, Design and Testing, pp. 73-78, 2000 https://doi.org/10.1109/MTDT.2000.868618
  13. Hamdioui, S., Rodgers, M., A. J. van de Goor, Eastwick, D., 'Realistic Fault Models and Test Procedure for Multi-Port SRAMs,' Memory Technology, Design and Testing, pp. 65-72, 2001 https://doi.org/10.1109/MTDT.2001.945230
  14. Hamdioui, S., A. J. van de Goor., 'Efficient Tests for Realistic Faults in Dual-Port SRAMs,' IEEE Transactions on, Computers, pp. 460-473, 2002 https://doi.org/10.1109/TC.2002.1004586