JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Stress and Stress Voiding in Cu/Low-k Interconnects

  • Paik, Jong-Min (Research Institute of Advanced Materials, Seoul National University) ;
  • Park, Hyun (School of Materials Science and Engineering, Seoul National University) ;
  • Joo, Young-Chang (School of Materials Science and Engineering, Seoul National University)
  • Published : 2003.09.01
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Abstract

Through comparing stress state of TEOS and SiLK-embedded structures, the effect of low-k materials on stress and stress distribution in via-line structures were investigated using three-dimensional finite element analyses. In the case of TEOS-embedded via-line structures, hydrostatic stress was concentrated at the via and the top of the lines, where the void was suspected to nucleate. On the other hand, in the via-line structures integrated with SiLK, large von-Mises stress is maintained at the via, thus deformation of via is expected as the main failure mode. A good correlation between the calculated results and experimentally observed failure modes according to dielectric materials was obtained.

Keywords

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