• 제목/요약/키워드: interconnection stress voiding

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Stress and Stress Voiding in Cu/Low-k Interconnects

  • Paik, Jong-Min;Park, Hyun;Joo, Young-Chang
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제3권3호
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    • pp.114-121
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    • 2003
  • Through comparing stress state of TEOS and SiLK-embedded structures, the effect of low-k materials on stress and stress distribution in via-line structures were investigated using three-dimensional finite element analyses. In the case of TEOS-embedded via-line structures, hydrostatic stress was concentrated at the via and the top of the lines, where the void was suspected to nucleate. On the other hand, in the via-line structures integrated with SiLK, large von-Mises stress is maintained at the via, thus deformation of via is expected as the main failure mode. A good correlation between the calculated results and experimentally observed failure modes according to dielectric materials was obtained.