한국정밀공학회지 (Journal of the Korean Society for Precision Engineering)
- 제13권12호
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- Pages.13-21
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- 1996
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- 1225-9071(pISSN)
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- 2287-8769(eISSN)
반도체 칩 캡슐화 공정에 있어서 와이어 스윕(wire sweep) 최소화에 관한 연구
Reduction of Wire Sweep during Chip Encapsulation by Runner Balancing and Ram Control
초록
In this paper, methods to reduce wire sweep during the chip-encapsulation process have been studide. Two methods have been tried for this purpose, namely runner balancing and ram velocity control. Runner balancing has been achieved automatically by using a computer program. Ram-velocity control has been achieved using empirical rules and results from a flow simulation of the encapsulation process. A mold which has 12 cavities for chip has been used as a case study. The simulation results show that the wire sweep obtained from the optimal process condition is about 1/5 of that from initial, unoptimized condition.
키워드