• 제목/요약/키워드: 와이어 스윕

검색결과 3건 처리시간 0.018초

반도체 칩 캡슐화 성형 공정에 있어서 와이어 스윕 및 패들 변형에 관한 연구 (A Study of Wire Sweep, Pre-conditioning and Paddle Shift during Encapsulation of Semiconductor Chips)

  • 한세진;허용정;이성철
    • 한국정밀공학회지
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    • 제18권2호
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    • pp.102-110
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    • 2001
  • In this paper, methods to analyze wire sweep and paddle shift during the semiconductor ship-encapsulation process have been studied. The analysis of wire sweep includes flow-field analysis in a complicated geometry, drag-force calculation for given flow of fluid, and wire-deformation calculation for given loads. The paddle-shift analysis is used to analyze the deformation of the paddle due to the pressure difference in two cavities. the analysis is done using either analytical solutions or numerical simulation. The analytical solution is used for rough but fast calculation of wire sweep. The numerical solution is used for more accurate calculation of wire-sweep. The numerical results of wire sweep show good agreements with the experimental ones.

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반도체 칩 캡슐화 공정에 있어서 와이어 스윕(wire sweep) 최소화에 관한 연구 (Reduction of Wire Sweep during Chip Encapsulation by Runner Balancing and Ram Control)

  • 한세진;허용정
    • 한국정밀공학회지
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    • 제13권12호
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    • pp.13-21
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    • 1996
  • In this paper, methods to reduce wire sweep during the chip-encapsulation process have been studide. Two methods have been tried for this purpose, namely runner balancing and ram velocity control. Runner balancing has been achieved automatically by using a computer program. Ram-velocity control has been achieved using empirical rules and results from a flow simulation of the encapsulation process. A mold which has 12 cavities for chip has been used as a case study. The simulation results show that the wire sweep obtained from the optimal process condition is about 1/5 of that from initial, unoptimized condition.

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반도체 칩의 캡슐화 성형을 위한 지식형 설계시스템에 관한 연구 (A Study on a Knowledge-Based Design System for Chip Encapsulation)

  • 허용정;한세진
    • 한국정밀공학회지
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    • 제15권2호
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    • pp.99-106
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    • 1998
  • In this paper, we have constructed an expert system for semiconductor chip encapsulation which combines a knowledge-based system with CAE software. The knowledge-base module includes heuristic and pre analysis knowledge for evaluation and redesign. Evaluation of the initial design and generation of redesign recommendations can be developed from the rules as applied to a given chip package. The CAE programs can be used for simulating the filling and packing stage of encapsulation process. The expert system is a new tool which enables package design or process conditions with high yields and high productivity.

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